參數(shù)資料
型號： PSD913F2
英文描述： 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7260 with optional Total Dose Rating of 300kRads
中文描述： 可配置的存儲系統(tǒng)級芯片的8位微控制器
文件頁數(shù)： 4/94頁
文件大?。?/td> 463K
代理商： PSD913F2
Preliminary
PSD913F1
3
J
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80186, 80C251, and 80386EX
Motorola 68HC11, 68HC16, 68HC12, and 683XX
Philips 8031 and 8051XA
Zilog Z80 and Z8
J
Internal 1 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
J
Internal secondary 256 Kbit EEPROM memory. It is divided into four equal-sized blocks
that can be accessed with user-specified addresses. This secondary memory brings
the ability to execute code and update the main Flash
concurrently.
J
16 Kbit scratchpad SRAM. The SRAM’s contents can be protected from a power failure
by connecting an external battery.
J
Optional 64 byte One Time Programmable (OTP) memory that can be used for product
configuration and calibration.
J
General purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
J
Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
J
27 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
16 of the I/O ports may be configured as open-drain outputs.
J
Standby current as low as 50 μA for 5 V devices, 25 μA for 3 V devices.
J
Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
J
Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
J
Internal programmable Power Management Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can automatically detect a lack of microcontroller
activity and put the PSD913F1 into Power Down Mode.
J
Erase/Write cycles:
Flash memory – 100,000 minimum
EEPROM – 10,000 minimum
PLD – 1,000 minimum
Data Retention: 15 year minimum at 90 degrees Celsius (for Main Flash, Boot, PLD
and Configuration bits).
2.0
Key Features
相關(guān)PDF資料
PDF描述
PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F2-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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