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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-681
15
RESET_PESMII
R/W
0
This bit resets the Serial MII logic.
14:13
-
0
Unused
12
PHY_MODE
R/W
1
This bit congures the Serial MII logic with the connecting SMII
device type. Set this bit when connecting to a SMII PHY. Clear this
bit when connecting to a SMII MAC. When MAC is selected, the
SMII will operate at 100 Mb/s, full duplex.
11
RESET_PERMII
R/W
0
This bit resets the Reduced MII logic.
10:9
-
0
Unused
8
SPEED
R/W
0
This bit congures the Reduced MII logic for the current operating
speed. When set, 100 Mb/s mode is selected. When cleared,
10 Mb/s mode is selected.
7
RESET_PE100X
R/W
0
This bit resets the PE100X module which contains the 4B/5B
symbol encipher/decipher logic. This effects the PE100X module
only.
6
FORCE_QUIET
R/W
0
When set, transmit data is quieted, which allows the contents of the
cipher to be output. When cleared, normal operation is enabled.
Effects PE100X module only.
5
NO_CIPHER
R/W
0
When set, the raw transmit 5B symbols are transmitted without
ciphering. When cleared, normal ciphering occurs. Effects PE100X
module only.
4
DISABLE_LINK_FAIL
R/W
0
When set, the 330ms Link Fail timer is disabled allowing for shorter
simulations. Removes the 330 mS link-up time before reception of
streams is allowed. When cleared, normal operation occurs.
Effects PE100X module only.
3
RESET_PE10T
R/W
0
This bit resets the PE10T module which converts MII nibble streams
to the serial bit stream of 10T transceivers. Effects PE10T module
only.
2
-
0
Unused
1
ENABLE_JABBER_
PROTECTION
R/W
0
This bit enables the Jabber Protection logic within the PE10T in
ENDEC mode.
Jabber is the condition where a transmitter is stuck
on for longer than 50ms to prevent other stations from transmitting.
Effects PE10T module only.
0
BIT_MODE
R/W
0
When set, the MAC is in 10BASE-T ENDEC mode, which changes
decodes (such as EXCESS_DEFER) to be based on the bit clock
rather than the nibble clock.
Offset 0x07 201C
Test Register (TEST)
31:3
-
0
Unused
2
TEST_
BACKPRESSURE
R/W
0
Setting this bit will cause the MAC to assert back pressure on the
link. Back pressure causes the preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during
back pressure.
1
TEST_PAUSE
R/W
0
This bit causes the MAC Control sublayer to inhibit transmissions,
just as if a PAUSE Receive Control frame with a non-zero pause
time parameter was received.
0
SHORTCUT_PAUSE_
QUANTA
R/W
0
This bit reduces the effective PAUSE Quanta from 64 byte-times to
1 byte-time.
Table 2: LAN100 Registers …Continued
Bit
Symbol
Acces
s
Value
Description