
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
15-525
16:8
WSDIV
R/W
0x0
Sets the divider used to derive WS from SCK. Set to 0...511 for a
serial frame length of 1...512.
Note the frame size limitations discussed in Section 23.4.6.1 on
page 23-16.
7:0
SCKDIV
R/W
0x0
Sets the divider used to derive SCK from OSCLK. Set to 0...255 for
division by 1...256.
Offset 0x11 000C
AO_FRAMING—DMA Clock Domain
31
POLARITY
R/W
0
0 = Serial frame starts with a WS negedge.
1 = Serial frame starts with a WS posedge.
This bit should not be changed during operation of Audio Out i.e.,
only update this bit when TRANS_ENABLE = 0.
30
SSPOS4
R/W
0
Start/Stop bit position MSB. Note that SSPOS is a 5-bit eld, while
bit SSPOS4 is non-adjacent for backwards compatibility in 16-bit/
sample modes. Program this eld along with AO_FRAMING[3:0].
29:22
Unused
-
To ensure software backward compatibility unused or reserved bits must
be written as zeros and ignored upon read
.
21:13
LEFTPOS
R/W
0x0
Denes the bit position within a serial frame where the rst data bit
of the left channel is placed. The rst bit of a serial frame is bit 0.
12:4
RIGHTPOS
R/W
0x0
Denes the bit position within a serial frame where the rst data bit
of the right channel is placed.
3:0
SSPOS
R/W
0x0
Start/Stop bit position. Note that SSPOS is a 5-bit eld, while bit
SSPOS4 is non-adjacent for backwards compatibility in 16-bit/
sample modes. Program this eld along with AO_FRAMING[30].
If DATAMODE = MSB rst, transmission starts with the MSB of the
sample i.e., bit 15 for 16-bit/sample modes or bit 31 for 32-bit/
sample modes. SSPOS determines the bit index (0..31) in the
parallel input word of the last transmitted data bit.
If DATAMODE = LSB rst, SSPOS determines the bit index (0..31)
in the parallel word of the rst transmitted data bit. Bits SSPOS up
to and including the MSB are transmitted i.e., up to bit 15 in 16-bit/
sample mode and bit 31 in 32-bit/sample mode.
Offset 0x11 0010
Reserved—DTL Clock Domain
31:0
Reserved
-
To ensure software backward compatibility unused or reserved bits must
be written as zeros and ignored upon read
.
Offset 0x11 0014
AO_BASE1—DTL Clock Domain
31:6
BASE1
R/W
0x0
Base Address of DMA buffer1 in memory - must be a 64-byte
aligned address in local memory.
If changed it must be set before ACK1.
5:0
Unused
-
To ensure software backward compatibility unused or reserved bits must
be written as zeros and ignored upon read
.
Offset 0x11 0018
AO_BASE2—DTL Clock Domain
31:6
BASE2
R/W
0x0
Base Address of DMA buffer2 in memory - must be a 64-byte
aligned address in local memory.
If changed it must be set before ACK2.
5:0
Unused
-
To ensure software backward compatibility unused or reserved bits must
be written as zeros and ignored upon read
.
Table 9: Audio Output Port Registers …Continued
Bit
Symbol
Acces
s
Value
Description