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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 8: General Purpose Input Output Pins
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
8-288
0x10,4090
BASE1_PTR3
Base address for DMA buffer 1 of FIFO queue 3.
0x10,4094
BASE2_PTR0
Base address for DMA buffer 2 of FIFO queue 0.
0x10,4098
BASE2_PTR1
Base address for DMA buffer 2 of FIFO queue 1.
0x10,409C
BASE2_PTR2
Base address for DMA buffer 2 of FIFO queue 2.
0x10,40A0
BASE2_PTR3
Base address for DMA buffer 2 of FIFO queue 3.
0x10,40A4
SIZE0
Size of queue 0 in bytes.
0x10,40A8
SIZE1
Size of queue 1 in bytes.
0x10,40AC
SIZE2
Size of queue 2 in bytes.
0x10,40B0
SIZE3
Size of queue 3 in bytes.
0x10,40B4
DIVIDER_0
Frequency divider for FIFO queue 0
0x10,40B8
DIVIDER_1
Frequency divider for FIFO queue 1
0x10,40BC
DIVIDER_2
Frequency divider for FIFO queue 2
0x10,40C0
DIVIDER_3
Frequency divider for FIFO queue 3
0x10,40C4
TSU0
Timestamp Unit 0.
0x10,40C8
TSU1
Timestamp Unit 1
0x10,40CC
TSU2
Timestamp Unit 2
0x10,40D0
TSU3
Timestamp Unit 3
0x10,40D4
TSU4
Timestamp Unit 4
0x10,40D8
TSU5
Timestamp Unit 5
0x10,40DC
TSU6
Timestamp Unit 6
0x10,40E0
TSU7
Timestamp Unit 7
0x10,40E4
TSU8
Timestamp Unit 8
0x10,40E8
TSU9
Timestamp Unit 9
0x10,40EC
TSU10
Timestamp Unit 10.
0x10,40F0
TSU11
Timestamp Unit 11
0x10,40F4
TIME_CTR
31-bit timestamp master time counter. Runs at 13.5 MHz (108 MHz/8).
0x10,40F8
TIMER_IO_SEL
Selects GPIO pins or internal signals to be use as inputs for internal TM3260 timers.
0x10,40FC
VIC_INT_STATUS
Combined Interrupt status register for the VIC interrupts
0x10,4100
DDS_OUT_SEL
Enables GPIO[14:12] pins to output clocks coming from the clock module.
0x10,4FA0
INT_STATUS0
Interrupt status register, combined with module status for FIFO queue 0
0x10,4FA4
INT_ENABLE0
Interrupt enable register for FIFO queue 0
0x10,4FA8
INT_CLEAR0
Interrupt clear register (by software) for FIFO queue 0
0x10,4FAC
INT_SET0
Interrupt set register (by software) for FIFO queue 0
0x10,4FB0
INT_STATUS1
Interrupt status register, combined with module status for FIFO queue 1
0x10,4FB4
INT_ENABLE1
Interrupt enable register for FIFO queue 1
0x10,4FB8
INT_CLEAR1
Interrupt clear register (by software) for FIFO queue 1
0x10,4FBC
INT_SET1
Interrupt set register (by software) for FIFO queue 1
0x10,4FC0
INT_STATUS2
Interrupt status register, combined with module status for FIFO queue 2
Table 6: Register Summary …Continued
Name
Description