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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
5-197
2:1
sel_clk_gpio_q6_12_ctl
R/W
00
00: clk_gpio_q6_12_ctl = 27 MHz xtal_clk
01: clk_gpio_q6_12_ctl = DDS6
10: clk_gpio_q6_12_ctl = 27 MHz xtal_clk
11: clk_gpio_q6_12_ctl = LAN_TXD[3]
0
en_clk_gpio_q6_12_ctl
R/W
1
1: enable clk_gpio_q6_12_ctl
Offset 0x04,740C
CLK_GPIO_13_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_gpio_13_ctl
R/W
00
00: clk_gpio_13_ctl = 27 MHz xtal_clk
01: clk_gpio_13_ctl = DDS5
10: clk_gpio_13_ctl = UNDEF
11: clk_gpio_13_ctl = LAN_RXD[0]
0
en_clk_gpio_13_ctl
R/W
1
1: enable clk_gpio_13_ctl
Offset 0x04,7410
CLK_GPIO_14_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_gpio_14_ctl
R/W
00
00: clk_gpio_14_ctl = 27 MHz xtal_clk
01: clk_gpio_14_ctl = DDS2
10: clk_gpio_14_ctl = UNDEF
11: clk_gpio_14_ctl = LAN_RXD[1]
0
en_clk_gpio_14_ctl
R/W
1
1: enable clk_gpio_14_ctl
Offset 0x04,7414
CLK_FGPO_CTL
31:9
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
8
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
7
Invert_fgpo_clock
R/W
0
Invert FGPO clock
0 : do not invert the clock
1: invert the clock only to the fgpo block and not to the pad.
6
fgpo_output_select
R/W
0
FGPO output select
0: Seperate output mode, The clock to the fgpo and to the pad
share the same source, but have seperate paths.
1: Feedback output mode, The clock is driven to the pad then is
feedback to the clock block. It then goes through gating logic to the
fgpo block.
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description