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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 19: Memory Based Scaler
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
19-586
Table 4 shows the opcodes allowed in a descriptor list. The data structure consists of
32 bit words; therefore, endian mode rules do apply. The command type is dened in
the lower two bits of the 32-bit word. The remaining bits are decoded depending on
the command type.
2.4.2
Video Source Controls
Source Video data for the MBS can be fetched via three dedicated DMA engines. It
can be fetched from memory in several packed or planar formats. The source window
is dened by one set of width and height values which are automatically translated
into the corresponding number of 64-bit words to be fetched per line for each plane.
Video lines can be fetched in a reverse order as well, thereby allowing horizontal
ipping of images for applications like video conferencing.
To allow fetching of interlaced video lines from different locations in memory, each
plane can be assigned a second set of base address registers. Pitches are dened
separately only for luma and chroma planes. The lower three bits of the rst three
base address registers are used as an intra-long-word offset for the leftmost pixel
components of each line. The offset has to be a multiple of the number of bytes per
component.
Fixed Input Formats
The xed input formats, as shown in
Table 5, consist of indexed, packed and planar
modes.
Table 4: Task Descriptor Opcode Table
Command
Bits
Function
Description
Jump
Link to address
25:3
address
Denes location where processing of commands continues.
1:0
opcode
= 00 (binary)
Exec/Stop
End of task list
2
stop ag
If this ag is set, processing of the MBS task is stopped.
1:0
opcode
= 01 (binary)
Queue
Start processing and queue next task
25:3
address
Task at this location is started after processing of current task nished.
1:0
opcode
= 10 (binary)
Load
Load register
31:24
count
Dene number of registers to be loaded minus one.
19:16
mask
Write mask, if bit is zero according byte is written, if bit is set byte is not
written.
11:2
Index
Load registers starting at offset.
1:0
opcode
= 11 (binary)