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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
3-120
6.
System Related Information for TM3260
This section contains information on how the internal TM3260 resources like its
interrupt lines or timers have been assigned or used in the PNX15xx/952x Series
system. More specic details on how to program or on the exact behavior of these
resources is found in [1].
6.1 Interrupts
A fundamental aspect of PNX15xx/952x Series system is to provide hardware
modules (or hardware accelerators) that relieve the TM3260 CPU for other video/
audio processing. These modules are mainly internal bus DMA masters. Thus once
programmed by the TM3260 they only require limited CPU processing power. For
example the video module only requires the TM3260 to update the pointers to the
next frame 60 times per seconds. An interrupt line is used to signal TM3260 of that
need.
The TM3260 Vectored Interrupt Controller (VIC) provides 64 inputs for interrupt
request lines. The interrupt controller prioritizes and maps the multiple requests from
the several PNX15xx/952x Series modules onto successive interrupt requests to the
TM3260 execution unit.
Table 5 shows the assignment of modules to interrupt source numbers, as well as the
recommended operating mode (edge or level triggered). Note that there are a total of
7 possible external pins to assert interrupt requests. Only PCI_INTA_N is a dedicated
pin for external interrupts. The other pins may be used for other functionality. The rst
5 interrupt sources, i.e. source 0 through 4, are asserted by active low signal
conventions, i.e. a zero level or a negative edge asserts a request. The remaining two
external interrupt lines, i.e. source 26 and 27, like all the other regular interrupt lines,
operate with active high signalling conventions.
31:0
SEMAPHORE14
R/W
0
Same as semaphore0 register.
Offset 0x06 383C
SEMAPHORE15
31:0
SEMAPHORE15
R/W
0
Same as semaphore0 register.
Table 4: Semaphore MMIO Registers …Continued
Bits
Symbol
Acces
s
Value
Description
Table 5: Interrupt Source Assignments
SOURCE NAME
SOURCE
NUMBER
INTERRUPT
OPERATING MODE
SOURCE DESCRIPTION
PCI_INTA_N
0
level
External PCI INTA interrupt used by the host CPU. Active
LOW
PCI_GNT_A_N
1
level
Direct external interrupt input line, active LOW
PCI_GNT_B_N
2
level
Direct external interrupt input line, active LOW
PCI_REQ_A_N
3
level
Direct external interrupt input line, active LOW
PCI_REQ_B_N
4
level
Direct external interrupt input line, active LOW
TIMER1
5
edge
General purpose internal TM3260 timer.
TIMER2
6
edge
General purpose internal TM3260 timer.