
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
7-265
27:21
Base18 Address
R/W*
1100000
*The base 18 can be congured to various aperture sizes from 2
MB to 256 MB. (See pci_setup register). Depending on aperture
size selected, various bits will be R/W or Read Only.
Bit:
27
26
25
24
23
22
21
256M:
RO
128M:
RW
RO
64M:
RW
RO
32M:
RW
RO
16M:
RW
RO
8M:
RW
RO
4M:
RW
RO
2M:
RW
RO = Read-only bits read back as zero.
20:4
Reserved
R
0
3
Prefetchable
R
cfg*
Prefetchable if congured as 1.
*Value is determined by pci_setup register.
2:0
Memory
R
0
This bit indicates type 0 memory aperture.
Offset 0x002C
Subsystem ID/Subsystem Vendor ID
The values used in this register will be loaded into the register before entertaining any transactions on the PCI bus. The boot
loader will initialize control register address 0x006C with the correct values.
31:16
Subsystem ID
R
0
Subsystem ID. The value for this eld is provided by NXP PCI SIG
representative for NXP internal customers. External customers will
provide their own number.
15:0
Subsystem Vendor ID
R
0
Subsystem Vendor ID. The value for this eld is 1131 for NXP
internal customers. External customers need to apply to the PCI
SIG to obtain a value if they do not have one already.
Offset 0x0030
Reserved
Offset 0x0034
Capabilities Pointer
31:8
Reserved
R
0
7:0
cap_pointer
R
0x40
Indicates extended capabilities are present starting at 40.
Offset 0x003C
Max_Lat, Min_Gnt, Interrupt pin, Interrupt Line
31:24
max_lat
R/W1
0x18
Indicates the max latency tolerated in 1/4 microsecond for PCI
master. This value may be changed if written to before the pci_setup
register.
23:16
min_gnt
R/W1
0x09
Indicates how long the PCI master will need to use the bus. This
value may be changed if written to before the pci_setup register.
15:8
interrupt_pin
R
0x01
Indicates which interrupt pin is used.
7:0
interrupt_line
R/W
0x00
Interrupt routing information
Offset 0x0040
Power Management Capabilities
31:27
Reserved
R
0x0000
26
d2_support
R
cfg*
1 = Device supports D2 power management state
*Value is determined by pci_setup register.
25
d1_support
R
cfg*
1 = Device supports D1 power management state
*Value is determined by pci_setup register.
24:19
Reserved
R
0
Table 9: PCI Conguration Registers
Bit
Symbol
Acces
s
Value
Description