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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 16: Audio Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
16-538
shows the required data bus arbitration latency requirements for a number of
common operating modes, for 2 channels. The right column in
Table 7 shows the
nature of the resulting 64-byte burst data bus requests.
In the Raw Mode however, the sampling is much faster. One eight bit byte is sampled
every SCK. Hence one 32 bit word (4 bytes) are transferred every four clocks. So for
example if the sample clock SCK is about 25 MHz, then the bandwidth requirement
would be 40 MBytes per second. Obviously this requirement is much higher than in
the usual serial mode for this block.
3.8 Error Behavior
If either an OVERRUN or HBE error occurs, input sampling is temporarily halted and
incoming samples will be lost. In the case of OVERRUN, sampling resumes as soon
as the control software makes one or more new buffers available through an ACK1 or
ACK2 operation. In the case of HBE, sampling will resume as soon as the data in the
FIFO can be written to memory. HBE and OVERRUN are ‘sticky’ error ags meaning
they will remain set until an explicit software write of logic ‘1’ to ACK_HBE or
3.9 Interrupts
The AI_STATUS register provides all sources of Audio In generated interrupt:
BUF1_FULL, BUF2_FULL, HBE and OVERRUN. All interrupts sourced by Audio In to
the chip level interrupt controller are level triggered. An interrupt will be generated
from Audio In only if the corresponding interrupt enable bit is set in the AI_CTL
register. For example, to assert an interrupt to the system upon the occurrence of a
bandwidth error (HBE asserted), set the HBE_INTEN bit to logic ‘1’. See
Section 4..Table 7: Audio In Data Bus Arbiter Latency Requirement Examples — 16-Bit Data Examples
CapMode
2 Channels
fs (kHz)
T (nS)
Max Arbiter Latency
(16*T) (uSec)
Access Pattern
Stereo
2x16 bits/sample
44.1
22,676
362.816
1 64-byte request
minimally every 362.816 uS
Stereo
2x16 bits/sample
48.0
20,833
333.328
1 64-byte request
minimally every 333.328 uS
Stereo
2x16 bits/sample
96.0
10,417
166.672
1 64-byte request
minimally every 166.672 uS
Table 8: Audio In Data Bus Arbiter Latency Requirement Examples — 32-Bit Data Examples
CapMode
2 Channels
fs (kHz)
T (nS)
Max Arbiter Latency
(8*T) (uSec)
Access Pattern
Stereo
2x32 bits/sample
44.1
22,676
181.408
1 64-byte request
minimally every 181.408uS
Stereo
2x32 bits/sample
48.0
20,833
166.66
1 64-byte request
minimally every 166.66 uS
Stereo
2x32 bits/sample
96.0
10,417
83.34
1 64-byte request
minimally every 83.34 uS