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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 8: General Purpose Input Output Pins
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
8-293
4.4 Sampling and Pattern Generation Control Registers for the FIFO
Queues
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
Bit
Symbol
Acces
s
Value
Description
Offset 0x10,4024 -> 0x030
GPIO_EV<0-3>
31
Unused
-
30
EN_EV_TSTAMP
R/W
0
Enables an event timestamp signal to be generated whenever the
last 32-bit word from a DMA buffer reaches the GPIO output pins.
This eld is only valid in Pattern Generating modes, i.e.
FIFO_MODE[1] set to ‘1’.
29
EN_IR_CARRIER
R/W
0
This bit enables a sub-carrier for Ir transmission. FREQ_DIV[15:0] is
combined with CARRIER_DIV[4:0] to generate sub-carrier and TX
frequencies:
0 - Ir Carrier disabled, CARRIER_DIV[4:0] not used.
1 - Ir Carrier enabled, CARRIER_DIV[4:0] used.
Note: This eld is only valid in Pattern Generation using samples
mode (FIFO_MODE=11) with EN_CLOCK_SEL disabled.
28
EN_IR_FILTER
R/W
0
This bit enables a received Ir signal to be ltered. No signal pulses
less than the period programmed in IR_FILTER are passed through
to the monitoring logic.
Note: This eld is only valid in Signal Sampling mode
(FIFO_MODE=01) with EN_CLOCK_SEL disabled.
27:26
EN_CLOCK_SEL
R/W
0
Enables an input signal selected by CLOCK_SEL to be used as the
external clock source:
00 - CLOCK_SEL disabled
10 - CLOCK_SEL disabled
01 - CLOCK_SEL enabled, sample on positive edge
11 - CLOCK_SEL enabled, sample on negative edge
Note: This eld is only valid in Signal Sampling mode
(FIFO_MODE=01) and Pattern Generation using samples mode
(FIFO_MODE=11).
25:24
EN_PAT_GEN_CLK
R/W
0
Enables the clock generated by the frequency divider to be sent out
of the chip during pattern generation using samples and frequency
divider mode:
00 - EN_PAT_GEN_CLK disabled
10 - EN_PAT_GEN_CLK disabled
01 - EN_PAT_GEN_CLK enabled, output the clock as is
11 - EN_PAT_GEN_CLK enabled, output the inverted clock
Note: This eld is only valid in Pattern Generation using samples
(FIFO_MODE=11) and frequency divider (EN_CLOCK_SEL -
disabled) mode
23:22
Unused