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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
18-579
8
UCBITS_SET
W
0
1 = UCBITS bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
7
LOCK_SET
W
0
1 = LOCK bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
6
VERR_SET
W
0
1 = VERR bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
5
PERR_SET
W
0
1 = PERR bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
4
OVR_SET
W
0
1 = OVERRUN bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
3
HBE_SET
W
0
1 = HBE bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
2
BUF1_ACTIVE_SET
W
0
1 = BUF1_ACTIVE bit in SPDI_STATUS is to be set to logic ‘1’.
Level trigger interrupt will be raised to the external interrupt
controller if the corresponding enable bit is set to logic ‘1’. 0 = No
effect
1
BUF2_FULL_SET
W
0
1 = BUF2_FULL bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
0
BUF1_FULL_SET
W
0
1 = BUF1_FULL bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
Offset 0x10 AFF4
SPDI_PWR_DWN
31
PWR_DWN
R/W
0
The bit is used to provide power control status for system software
block power management.
30:0
Unused
-
The PWR_DWN register is provided for software use only. The PWR_DWN bit has no functionality internal to the SPDI Input
module. The bit is used to provide power control status for system software block power management. The default power on
state of this bit is logic ‘0’.
Offset 0x10 AFFC
SPDI_MODULE_ID
31:16
Module ID
R
0x0110
This eld identies the block as type SPDIF Input.
SPDIF Input ID = 0x0110.
15:12
MAJ_REV
R
0
Major Revision ID
11:8
MIN_REV
R
0x1
Minor Revision ID
7:0
APERTURE
R
0
Aperture size
The MODULE_ID register allows software identication of the SPDIF Input module. The values found in the MODULE_ID
register will change with each version of the SPDIF Input module.
Table 6: SPDIF Input Registers …Continued
Bit
Symbol
Acces
s
Value
Description