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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
3-130
6
VDO_MODE
R/W
0
‘0’: No action
‘1’: When VDO_MODE[2:0] = 100, i.e. digital 24-bit YUV or RGB
video:
QVCP_DATA[15:12,9:2]
-> VDO_D[16:5] when VDO_CLK1=1
QVCP_DATA[29:22,19:16]
-> VDO_D[16:5] when VDO_CLK1=0
i.e. G[3:0], B[7:0]
-> VDO_D[16:5] when VDO_CLK1=1
i.e. R[7:0], G[7:4]
-> VDO_D[16:5] when VDO_CLK1=0
i.e. U[3:0], V[7:0]
-> VDO_D[16:5] when VDO_CLK1=1
i.e. Y[7:0], U[7:4]
-> VDO_D[16:5] when VDO_CLK1=0
All the other VDO pins are mapped as described below for
VDO_MODE[2:0] = 100.
This mode is typically used to interface with Video Encoders like the
NXP SAA7104 that require the video data to be presented on both
edges of the pixel clock. This mode allows to transfer the 24-bit data
over a 12-bit interface, VDO_D[16:5].
Note: The YUV mode does not match the SAA7104 expected
inputs. Use the RGB mode instead.
Note: This mode requires a 50/50 duty cycle clock. This can be
achieved by programming the QVCP PLL at twice the speed and
divide it by 2 by setting the P divider to 1, or use a times 4 or 8 as
5
VDO_MODE
R/W
0
‘0’: No action
‘1’: When VDO_MODE[2:0] = 010, i.e. digital 16-bit YUV video:
QVCP_DATA[19:12] -> VDO_D[20:13] when VDO_CLK1=1
QVCP_DATA[9:2]
-> VDO_D[20:13] when VDO_CLK1=0
i.e. UV[7:0]
-> VDO_D[20:13] when VDO_CLK1=1
i.e. Y[7:0]
-> VDO_D[20:13] when VDO_CLK1=0
All the other VDO pins are mapped as described below for
VDO_MODE[2:0] = 010.
This mode is typically used to interface with Video Encoders like the
NXP SAA7104 that require the video data to be presented on both
edges of the pixel clock. This mode allows to transfer the 16-bit data
over an 8-bit interface, VDO_D[20:13].
Note: This mode requires a 50/50 duty cycle clock. This can be
achieved by programming the QVCP PLL at twice the speed and
divide it by 2 by setting the P divider to 1, or use a times 4 or 8 as
4:3
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Table 8: Global Registers …Continued
Bit
Symbol
Acces
s
Value
Description