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| 型號(hào)： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁(yè)數(shù)： | 76/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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76
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Pin Information
(continued)
Table 42. Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins
(Can also be used as a general I/O)
M[3:0]
I
During powerup and initialization, M0—M3 are used to select the configuration mode with
their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O.*
PLL_CK[0:7]
I/O Dedicated PCM clock pins. These pins are a user-programmable I/O pins if not used by
PLLs
P[TBTR]CLK[1:0][
TC]
pairing. They may be used as general I/O pins if not needed for clocking purposes.
TDI, TCK, TMS
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select
inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once
configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be
held at logic 1 during configuration. Each pin has a pull-up enabled during configuration.
I/O After configuration, these pins are user-programmable I/O.*
RDY/BUSY/RCLK
O
During configuration in peripheral mode, RDY/RCLK indicates another byte can be written
to the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
I/O During the master parallel configuration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
HDC
O
High during configuration is output high until configuration is complete. It is used as a con-
trol output, indicating that configuration is not complete.
I/O After configuration, this pin is a user-programmable I/O pin.*
LDC
O
Low during configuration is output low until configuration is complete. It is used as a control
output, indicating that configuration is not complete.
I/O After configuration, this pin is a user-programmable I/O pin.*
INIT
I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up
is enabled, but an external pull-up resistor is recommended. As an active-low open-drain
output, INIT is held low during power stabilization and internal clearing of memory. As an
active-low input, INIT holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.*
CS0, CS1
I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During con-
figuration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O pins.*
RD/MPI_STRB
I
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7
into a status output. As a status indication, a high indicates ready, and a low indicates busy.
WR and RD should not be used simultaneously. If they are, the write strobe overrides.
This pin is also used as the MPI data transfer strobe.
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
I/O Pins dedicated for the primary clock. Input pins on the middle of each side with differential
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