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| 型號(hào)： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁(yè)數(shù)： | 46/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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46
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Special Function Blocks
(continued)
5-5971(F)
Figure 30. Instruction Register Scan Timing Diagram
TCK
TMS
TDI
R
R
E
E
U
S
C
S
T
S
P
S
E
Readback Logic
The readback logic can be enabled via a bit stream
option or by instantiation of a library readback compo-
nent.
Readback is used to read back the configuration data
and, optionally, the state of all PFU and PIO FF out-
puts. A readback operation can be done while the
FPGA is in normal system operation. The readback
operation can be daisy-chained. To use readback, the
user selects options in the bit stream generator in the
ORCA Foundry development system.
Table 25 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Table 25. Readback Options
Readback can be performed via the Series 4
MPI
or by
using dedicated FPGA readback controls. If the
MPI
is
enabled, readback via the dedicated FPGA readback
logic is disabled. Readback using the
MPI
is discussed
in the
MPI
section.
The pins used for dedicated readback are readback
data (RD_DATA), read configuration (
RD_CFG
), and
configuration clock (CCLK). A readback operation is ini-
tiated by a high-to-low transition on
RD_CFG
. The
RD_CFG
input must remain low during the readback
operation. The readback operation can be restarted at
frame 0 by driving the
RD_CFG
pin high, applying at
least two rising edges of CCLK, and then driving
RD_CFG
low again. One bit of data is shifted out on
RD_DATA at the rising edge of CCLK. The first start bit
of the readback frame is transmitted out several cycles
after the first rising edge of CCLK after
RD_CFG
is input
low (see the readback timing characteristics table in the
timing characteristics section). To be certain of the start
of the readback frame, the data can be monitored for
the 01 frame start bit pair.
Option
Function
0
1
U
Prohibit Readback
Allow One Readback Only
Allow Unrestricted Number of Readbacks
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