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參數(shù)資料
| 型號： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 32/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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32
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
On the output side of each PIO, an output from the PLC
array can be routed to each output FF, and logic can be
associated with each I/O pad. The output logic associ-
ated with each pad allows for multiplexing of output sig-
nals and other functions of two output signals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The out-
put buffer signal can be inverted, and the 3-state con-
trol can be made active-high, active-low, or always
enabled. In addition, this 3-state signal can be regis-
tered or nonregistered.
The Series 4 I/O logic has been enhanced to include
modes for speed uplink and downlink capabilities.
These modes are supported through shift register logic
which divides down incoming data rates or multiplies
up outgoing data rates. This new logic block also sup-
ports high-speed DDR mode requirements where data
is clocked into and out of the I/O buffers on both edges
of the clock.
The new programmable I/O cell allows designers to
select I/Os that meet many new communication stan-
dards permitting the device to hookup directly without
any external interface translation. They support tradi-
tional FPGA standards as well as high-speed single-
ended and differential pair signaling (as shown in
Table 14). Based on a programmable, bank-oriented
I/O ring architecture, designs can be implemented
using 3.3 V, 2.5 V, 1.8 V, and 1.5 V output levels.
Table 14. Series 4 Programmable I/O Standards
Note: Interfaces to DDR and ZBT memories are supported through the interface standards shown above.
Standard
LVTTL
LVCMOS2
LVCMOS1.8
PCI
LVDS
Bused-LVDS
V
DDIO
(V) V
REF
(V)
3.3
2.5
1.8
3.3
2.5
2.5
Interface Usage
NA
NA
NA
NA
NA
NA
General purpose.
PCI.
Point to point and multidrop backplanes, high noise immunity.
Network backplanes, high noise immunity, bus architecture
backplanes.
Network backplanes, differential 100 MHz+ clocking, optical
transceiver, high-speed networking.
Backplanes.
Backplane or processor interface.
LVPECL
2.5
NA
PECL
GTL
GTL+
3.3
3.3
3.3
1.5
1.5
3.3
2.5
2.0
0.8
1.0
0.75
0.9
1.5
1.25
HSTL-Class I
HTSL-Class III and IV
STTL3-Class I and II
SSTL2-Class I and II
High-speed SRAM and networking interfaces.
Synchronous DRAM interface.
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