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參數(shù)資料
| 型號(hào)： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁(yè)數(shù)： | 33/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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Lucent Technologies Inc.
33
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
The PIOs are located along the perimeter of the device.
The PIO name is represented by a two-letter designa-
tion to indicate on which side of the device it is located
followed by a number to indicate in which row or column
it is located. The first letter, P designates that the cell is
a PIO and not a PLC. The second letter indicates the
side of the array where the PIO is located. The four
sides are left (L), right (R), top (T), and bottom (B). The
individual I/O pad is indicated by a single letter (either
A, B, C, or D) placed at the end of the PIO name. As an
example, PL10A indicates a pad located on the left side
of the array in the tenth row.
Each PIC interfaces to four bond pads and contains the
necessary routing resources to provide an interface
between I/O pads and the PLCs. Each PIC is com-
posed of four programmable I/Os and significant routing
resources. Each PIC contains input buffers, output buff-
ers, routing resources, latches/FFs, and logic and can
be configured as an input, output, or bidirectional
I/O. Any PIO is capable of supporting the I/O standard
listed in Table 12 and supporting DDR and ZBTspecifi-
cations.
The I/O on the OR4Exxx Series devices allows compli-
ance with PCI Local Bus (Rev. 2.2) 3.3 V signaling
environments. The signaling environment used for
each input buffer can be selected on a per-pin basis.
The selection provides the appropriate I/O clamping
diodes for PCI compliance.
The CIBs that bound the PIOs have significant local
routing resources, similar to routing in the PLCs. This
new routing increases the ability to fix user pinouts
prior to placement and routing of a design and still
maintain routability. The flexibility provided by the rout-
ing also provides for increased signal speed due to a
greater variety of optimal signal paths.
Included in the PIO routing interface is a fast path from
the input pins to the PFU logic. This feature allows for
input signals to be very quickly processed by the SLIC
decoder function and used on-chip or sent back off of
the FPGA. Also, the Series 4 PIOs include latches and
FFs and options for using fast, dedicated secondary,
and edge clocks.
A diagram of a single PIO is shown in Figure 22, and
Table 15 provides an overview of the programmable
functions in an I/O cell.
5-9732(F)
Figure 22. Series 4 PIO Image from ORCAFoundry
OUTSH
OUTDDMUX
OUTDD
OUTFFMUX
OUTFF
CLK4MUX
EC
SC
CE
LSRMUX
LSR
GSR
ENABLED
DISABLED
SRMODE
CE_OVER_LSR
LSR_OVER_CE
ASYNC
CEMUX0
OUTDD
CLK
OUTSH
CLK
OUTDD
OUTREG
OUTREG
DO
CK
SP
LSR
AND
NAND
OR
NOR
XOR
XNOR
PLOGIC
PMUX
OUTSHMUX
BUFMODE
SLEW
FAST
LEVELMODE
LVCMOS18
PCI
SSTL2
SSTL3
HSTL
GTL
GTLPLUS
PECL
LVPECL
LVDS
P2MUX
OUTDD
TSMUX
USRTS
TSREG
DO
CK
LSR
RESET
SET
PULLMODE
UP
DOWN
NONE
INMUX
CEMUXI
NORMAL
INVERTED
LATCHFF
D0
D1
CK
SP
LSR
D0
CK
LATCHFF
LATCH
FF
INDDMUX
INDD
INCK
INFF
RESET
SET
RESET
SET
1
0
0
0
0
1
EC
SC
DELAY
CELL
IOPAD
OUTMUX
CE
1
LVTTL
LVCMOS2
DEL0
DEL1
DEL2
DEL3
DEL0
DEL1
DEL2
DEL3
MILLIAMPS
SIX
TWELVE
TWENTYFOUR
RESISTOR
OFF
ON
KEEPERMODE
OFF
ON
LATCH
FF
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