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| 型號(hào)： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 37/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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Lucent Technologies Inc.
37
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
LVDS I/O
The LVDS differential pair I/O standard allows for high-speed, low-voltage swing and low-power interfaces defined
by industry standards: ANSI*/TIA/EIA
-644 and IEEE 1596.3 SSI-LVDS. The general-purpose standard is supplied
without the need for an input reference supply and uses a low switching voltage which translates to low ac power
dissipation.
The ORCA LVDS I/O provides an integrated 100
matching resistor used to provide a differential voltage across
the inputs of the receiver. The on-chip integration provides termination of the LVDS receiver without the need of dis-
crete external board resistors. The user has the programmable option to enable termination per receiver pair for
point-to-point applications or, in multipoint interfaces, limit the use of termination to bused pairs. If the user chooses
to terminate any differential receiver, a single LVDS_R pin is dedicated to connect a single 100
resistor to V
SS
,
which will provide a balance termination to all of the LVDS receiver pairs programmed to termination. See Table 20
for the LVDS termination pin location.
Table 19 provides the dc specifications for the ORCA LVDS solution.
Table 19. LVDS I/O Specifications
Table 20. LVDS Termination Pin
PIO Downlink/Uplink
Each group of four PIO have access to an input/output shift register as shown in Figure 24. This feature allows high-
speed input data to be divided down by 1/2 or 1/4, and output data can be multiplied by 2x or 4x its internal speed.
Both the input and output shift can be programmed to operate at the same time. However, the same PIO cannot be
used for both input and output shift registers at the same time.
For input shift mode, the data from INDD from the PIO is connected to the input shift register. The input data is
divided down and is returned to the routing through the INSH nodes. In 4x mode, all the INSH nodes are used. 2x
mode uses INSH4 and INSH3. Similarly, the output shift register brings data into the register from dedicated
OUTSH nodes. 4x mode uses all the OUTSH signals. However, only OUTSH2 and OUTSH1 are used for 2x mode.
* ANSI is a registered trademark of American National Standards Institute, Inc.
EIA is a registered trademark of Electronic Industries Association.
Parameter
Min
95
0.0
–100
1.125
0.2
Typical
100
—
—
1.25
1.25
Max
105
2.4
100
1.375
2.2
Unit
V
mV
V
V
Built-in Receiver Differential Input Resistor
Receiver Input Voltage
Differential Input Threshold
Output Common-mode Voltage
Input Common-mode Voltage
Dedicated Chip LVDS External Termination Pin (LVDS_R) Per Package
BA352
AC3
BC432
AH29
BM680
AL1
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| OR4E2-1BC432 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| OR4E2-1BM680 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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