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| 型號： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 11/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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Lucent Technologies Inc.
11
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Logic Cells
(continued)
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus
into LUT memory.
Table 3 lists the basic operating modes of the LUT. Figure 4—Figure 7 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode’s use for generating logic.
Table 3. Look-Up Table Operating Modes
PFU Control Inputs
Each PFU has eight routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The eight control inputs are CLK[1:0], LSR[1:0], CE[1:0], and SEL[1:0],
and their functionality for each logic mode of the PFU is shown in Table 4. The clock signal to the PFU is CLK, CE
stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as syn-
chronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal
itself. SEL is used to dynamically select between direct PFU input and LUT output data as the input to
the latches/FFs.
All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable
indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from
GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs or the LUT outputs are always input to the latches/
FFs.
Table 4. Control Input Functionality
Mode
Logic
Function
4-, 5-, and 6-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct
input to ninth FF or as pass through to COUT.
Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode;
CIN and ninth FF for logic or ripple functions.
All LUTs combined to perform ripple-through data functions. Eight LUT registers available for
direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of
ripple mode are adder/subtractor, counter, multiplier, and comparator.
All LUTs and latches/FFs used to create a 32x4 synchronous dual-port RAM. Can be used as
single-port or as ROM.
Half Logic/
Half Ripple
Ripple
Memory
Mode
Logic
CLK[1:0]
LSR[1:0]
CE[1:0]
SEL[1:0]
CLK to all latches/
FFs
LSR to all latches/FFs,
enabled per nibble and
for ninth FF
LSR to all latches/FF,
enabled per nibble and
for ninth FF
LSR to all latches/FFs,
enabled per nibble and
for ninth FF
LSR0 port enable 2
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE1 RAM write enable
CE0 Port enable 1
Not used
Select between LUT
input and direct input for
eight latches/FFs
Select between LUT
input and direct input for
eight latches/FFs
Select between LUT
input and direct input for
eight latches/FFs
Not used
Half Logic/
Half Ripple
CLK to all latches/
FFs
Ripple
CLK to all latches/
FFs
Memory
(RAM)
Memory
(ROM)
CLK to RAM
Optional for
synchronous outputs
Not used
Not used
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