參數(shù)資料
型號: OR4E2
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述: 現(xiàn)場可編程門陣列(現(xiàn)場可編程門陣列)
文件頁數(shù): 6/132頁
文件大?。?/td> 2667K
代理商: OR4E2
6
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Product Description
Architecture Overview
The ORCA Series 4 architecture is a new generation of
SRAM-based programmable devices from Lucent
Technologies Microelectronics Group. It includes
enhancements and innovations geared toward today’s
high-speed systems on a single chip. Designed with
networking applications in mind, the Series 4 family
incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA Series 4 devices contain many new patented
enhancements and are offered in a variety of packages
and speed grades.
The hierarchical architecture of the logic, clocks, rout-
ing, RAM and system-level blocks create a seamless
merge of FPGA and ASIC designs. Modular hardware
and software technologies enable system-on-chip inte-
gration with true plug and play design implementation.
The architecture consists of four basic elements: pro-
grammable logic cells (PLCs), programmable input/out-
put cells (PIOs), embedded block RAMs (EBRs), and
system-level features. These elements are intercon-
nected with a rich routing fabric of both global and local
wires. An array of PLCs and its associated resources
are surrounded by common interface blocks (CIBs)
which provide an abundant interface to the adjacent
PIOs or system blocks. Routing congestion around
these critical blocks is eliminated by the use of the
same routing fabric implemented within the program-
mable logic core. PICs provide the logical interface to
the PIOs which provide the boundary interface off and
onto the device. Also, the interquad routing blocks (hIQ,
vIQ) separate the quadrants of the PLC array and pro-
vide the global routing and clocking elements. Each
PLC contains a PFU, SLIC, local routing resources,
and configuration RAM. Most of the FPGA logic is per-
formed in the PFU, but decoders, PAL-like functions,
and 3-state buffering can be performed in the SLIC.
The PIOs provide device inputs and outputs and can
be used to register signals and to perform input demul-
tiplexing, output multiplexing, uplink and downlink func-
tions, and other functions on two output signals.
The Series 4 architecture integrates macrocell blocks
of memory known as EBR. The blocks run horizontally
across the PLC array and provide flexible memory
functionality. Large blocks of 512x18 quad-port RAM
complement the existing distributed PFU memory. The
RAM blocks can be used to implement RAM, ROM,
FIFO, multiplier, and CAM.
System-level functions such as a microprocessor inter-
face, PLLs, embedded system bus elements (located in
the corners of the array), the routing resources, and
configuration RAM are also integrated elements of the
architecture.
相關(guān)PDF資料
PDF描述
OR4E4 Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
OR4E6 Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
ORT4622 Field-Programmable System Chip (FPSC) Four Channel x 622 Mbits/s Backplane Transceiver(現(xiàn)場可編程系統(tǒng)芯片(四通道x 622 M位/秒背板收發(fā)器))
ORT8850 Field-Programmable System Chip(現(xiàn)場可編程系統(tǒng)芯片)
OS8740230 Si Optical Receiver, 40 - 870MHz, 225mA max. @ 24VDC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E2-1BA256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BA416 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BC432 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BM680 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA