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| 型號(hào)： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 48/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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48
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Microprocessor Interface (MPI)
The Series 4 FPGAs have a dedicated synchronous MPI function block. The MPI is programmable to operate with
PowerPCMPC860/MPC8260 series microprocessors. The pin listing is shown in Table 26. The MPI implements an
8-, 16-, or 32-bit interface with 4-bit parity to the host processor (PowerPC) that can be used for configuration and
readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In
addition to dedicated-function registers, the MPI bridges to the AMBAembedded system bus through which the
PowerPCbus master can access the FPGA configuration logic, EBR, and other user logic. There is also capability
to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the
embedded system bus.
The control portion of the MPI is available following powerup of the FPGA if the mode pins specify MPI mode, even
if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus
can be 1-, 2-, or 4- bit. In configuration mode, the data bus width and parity are related to the state of the M[0:3]
mode pins. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI
library element in your design from the ORCAmacro library, or by setting the bit of the MPI configuration control
register prior to the start of configuration. The user can also enable and disable the parity bus through the configu-
ration bit stream. These pads can be used as general I/O when they are not needed for MPI use.
The ORCAFPGA is a memory-mapped peripheral to the PowerPCprocessor. The MPI interfaces to the user-pro-
grammable FPGA logic using the AMBAembedded system bus. The MPI has access to a series of addressable
registers made accessible by the AMBAsystem bus that provide FPGA control and status, configuration and read-
back data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits
wide. The address map for these registers and the user-logic address space utilize the same registers as the
AMBAembedded system bus. The internal AMBAbus is 32 bits wide and the proper transformation of 8-, 16-, or
32-bit data of the MPI is done when transferring data between the MPI and ESB.
Table 26. MPC 860 to ORCAMPI Interconnection
PowerPC
Signal
ORCAPin
Name
MPI
I/O
Function
D[n:0]
DP[m0]
A[14:31]
TS
BURST
D[31:0]
DP[3:0]
A[17:0]
MPI_STRB
MPI_BURST
I/O
I/O
I
I
I
8-, 16-, 32-bit data bus.
Selectable parity bus width from 1-, 2-, and 4-bit.
32-bit MPI address bus.
Transfer start signal.
Active-low indicates burst transfer in-progress/High indicates current transfer
not a burst.
Active-low MPI select.
Active-high MPI select.
PowerPC interface clock.
Read (high)/write (low) signal.
Active-low transfer acknowledge signal.
Active-low burst transfer in progress signal indicates that the second beat in
front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
Active-low interrupt request signal.
—
—
CS0
CS1
I
I
I
I
CLKOUT
RD/WR
TA
BDIP
MPI_CLK
MPI_RW
MPI_ACK
MPI_BDIP
O
O
Any of
IRQ[7:0]
TEA
MPI_IRQ
O
MPI_TEA
O
Active-low indicates MPI detects a bus error on the internal system bus for
current transaction.
Requests the MPC860 to relinquish the bus and retry the cycle.
RETRY
MPI_RTRY
O
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