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| 型號(hào)： | OR4E2 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 41/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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Lucent Technologies Inc.
41
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Special Function Blocks
(continued)
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 25, the con-
nections between U1 and U2 (shown by nets a, b,
and c) can be tested by driving a value onto the given
nets from one device and then determining whether this
same value is seen at the other device. This is deter-
mined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin. Then,
based upon the value of the 3-state signal, either the
I/O pad is driven to the value given in the BSR, or the
BSR is updated with the input value from the I/O pad,
which allows it to be shifted out TDO.
The SAMPLE and PRELOAD instructions are useful for
system debugging and fault diagnosis by allowing the
data at the FPGA’s I/Os to be observed during normal
operation or written during test operation. The data for
all of the I/Os is captured simultaneously into the BSR,
allowing them to be shifted-out TDO to the test host.
Since each I/O buffer in the PIOs is bidirectional, two
pieces of data are captured for each I/O pad: the value
at the I/O pad and the value of the 3-state control sig-
nal. For preload operation, data is written from the BSR
to all of the I/Os simultaneously.
There are six ORCA-defined instructions. The PLC
scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user-
defined internal scan paths using the PLC latches/FFs
and routing interface. The RAM_Write Enable
(RAM_W) instruction allows the user to serially config-
ure the FPGA through TDI. The RAM_Read Enable
(RAM_R) allows the user to read back RAM contents
on TDO after configuration. The IDCODE instruction
allows the user to capture a 32-bit identification code
that is unique to each device and serially output it at
TDO. The IDCODE format is shown in Table 23.
An optional IEEE 1149.3 instruction RUNBIST has
been implemented. This instruction is used to invoke
the built-in self-test (BIST) of regular structures like
RAMs, ROMs, FIFOs, etc., and the surrounding RAN-
DOM logic in the circuit.
Also implemented in Series 4 devices is the IEEE
1532/D1 standards for in-system configuration for pro-
grammable logic devices. Included are four mandatory
and two optional instructions defined in the standards.
ISC_ENABLE, ISC_PROGRAM, ISC_NOOP and
ISC_DISABLE are the four mandatory instructions.
ISC_ENABLE initializes the devices for all subsequent
ISC instructions. The ISC_PROGRAM instruction is
similar to the RAM_WRITE instruction implemented in
all ORCAdevices where the user must monitor the
PINITN pin for a high indicating the end of initialization
and a successful configuration can be started. The
ISC_PROGRAM instruction is used to program the
configuration memory through a dedicated ISC_Pdata
register. The ISC_NOOP instruction is used when pro-
gramming multiple devices in parallel. During this
mode, TDI and TDO behave like BYPASS. The data
shifted through TDI is shifted out through TDO. How-
ever, the output pins remain in control of the BSR,
unlike BYPASS where they are driven by the system
logic. The ISC_DISABLE is used upon completion of
the ISC programming. No new ISC instructions will be
operable without another ISC_ENABLE instruction.
Optional 1532/D1 instructions include
ISC_PROGRAM_USERCODE. When this instruction
is loaded, the user shifts all 32 bits of a user-defined ID
(LSB first) through TDI. This overwrites any ID previ-
ously loaded into the ID register. This ID can then be
read back through the USERCODE instruction defined
in IEEE1149.2.
ISC_READ is similar to the ORCARAM_Read instruc-
tion which allows the user to read back the configura-
tion RAM contents serially out on TDO. Both must
monitor the PDONE signal to determine weather or not
configuration is completed. ISC_READ used a 1-bit
register to synchronously read back data coming from
the configuration memory. The readback data is
clocked into the ISC_READ data register and then
clocked out TDO on the falling edge or TCK.
Table 23. Series 4E Boundary-Scan Vendor-ID Codes
* PLC array size of FPGA, reverse bit order.
Note: Table assumes version 0.
Device
OR4E2
OR4E4
OR4E6
OR4E10
OR4E14
Version (4-bit)
0000
0000
0000
0000
0000
Part
*
(10-bit)
0011100000
0001010000
0000110000
0011110000
0010001000
Family (6-bit)
001000
001000
001000
001000
001000
Manufacturer (11-bit)
00000011101
00000011101
00000011101
00000011101
00000011101
LSB (1-bit)
1
1
1
1
1
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