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參數(shù)資料
| 型號(hào)： | MT48LC32M4A2P-7ELIT:G |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 9/74頁(yè) |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
17
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Functional Description
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
by A1–A9, A11 (x4), A1–A9 (x8), or A1–A8 (x16) when BL = 2; by A2–A9, A11 (x4), A2–A9
(x8), or A2–A8 (x16) when BL = 4; and by A3–A9, A11 (x4), A3–A9 (x8), or A3–A8 (x16)
when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap within the page if the boundary
is reached.
Burst Type
Accesses within a given burst may be programmed either to be sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 5 on page 19.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC32M4A2TG | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC32M4A2TG-75 | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC32M4A2TG-75IT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:SYNCHRONOUS DRAM |
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