參數(shù)資料
型號： MT48LC32M4A2P-7ELIT:G
元件分類： DRAM
英文描述： 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù)： 24/74頁
文件大?。?/td> 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
30
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
desired data element is valid, where x = CL - 1. This is shown in Figure 17 for each
possible CL; data element n + 3 is either the last of a burst of four or the last desired of a
longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 18 on page 31 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 17:
READ-to-PRECHARGE
Notes:
1. DQM is LOW.
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
PRECHARGE
ACTIVE
t RP
T7
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
X = 1 cycle
CL = 2
CL = 3
X = 2 cycles
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
TRANSITIONING DATA
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
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