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參數(shù)資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 35/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
40
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
Figure 32:
WRITE With Auto Precharge Interrupted by a READ
Notes:
1. DQM is LOW.
Figure 33:
WRITE With Auto Precharge Interrupted by a WRITE
Notes:
1. DQM is LOW.
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANKn
NOP
DIN
a + 1
DIN
a
NOP
T7
BANK n
BANK m
ADDRESS
BANK n,
COL a
BANK m,
COL d
READ - AP
BANKm
Internal
States
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
tRP - BANK m
DOUT
d
DOUT
d + 1
CL = 3 (BANK m)
tRP - BANK n
tWR - BANK n
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANKn
NOP
DIN
d + 1
DIN
d
DIN
a + 1
DIN
a + 2
DIN
a
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANKm
Internal
States
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
tWR - BANK n
tRP - BANK n
tWR - BANK m
TRANSITIONING DATA
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