參數(shù)資料
型號(hào)： MT48LC32M4A2P-7ELIT:G
元件分類： DRAM
英文描述： 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù)： 33/74頁
文件大?。?/td> 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
39
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Figure 30:
READ With Auto Precharge Interrupted by a READ
Notes:
1. DQM is LOW.
Figure 31:
READ With Auto Precharge Interrupted by a WRITE
Notes:
1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN at T4.
WRITE with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 32 on page 40).
DON’T CARE
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANKn
NOP
DOUT
a + 1
DOUT
d
DOUT
d + 1
NOP
T7
BANK n
CL = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
BANK n,
COL a
BANK m,
COL d
READ - AP
BANKm
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK n
tRP - BANKm
CL = 3 (BANK n)
TRANSITIONING DATA
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
DIN
d + 1
DIN
d
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM1
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANKm
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP - BANK n
t WR -BANK m
CL = 3 (BANK n)
READ - AP
BANKn
DON’T CARE
TRANSITIONING DATA
DOUT
a
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