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參數資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數： | 21/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
28
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Figure 14:
Random READ Accesses
Notes:
1. Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 15 on page 29 and
Figure 16 on page 29. The DQM signal must be asserted (HIGH) at least 2 clocks prior to
the WRITE command (DQM latency is 2 clocks for output buffers) to suppress data-out
from the READ. After the WRITE command is registered, the DQ will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 in Figure 16, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6
would be invalid.
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DON’T CARE
DOUT
n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
DOUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CL = 2
CL = 3
TRANSITIONING DATA
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