參數(shù)資料
型號(hào)： MT48LC32M4A2P-7ELIT:G
元件分類： DRAM
英文描述： 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 26/74頁(yè)
文件大小： 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
32
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Figure 19:
WRITE Command
Figure 20:
WRITE Burst
Notes:
1. BL = 2. DQM is LOW.
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 21 on page 33. Data n + 1 is either the
last of a burst of two or the last desired element of a longer burst. The 128Mb SDRAM
uses a pipelined architecture and, therefore, does not require the 2n rule associated with
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A10
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A0–A9, A11: x4
A0–A9: x8
A0–A8: x16
A11: x8
A9, A11: x16
BA0, BA1
BANK
ADDRESS
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
DON’T CARE
WRITE
DIN
n + 1
NOP
BANK,
COL n
TRANSITIONING DATA
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