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參數(shù)資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 27/74頁 |
| 文件大?。?/td> | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
33
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
a prefetch architecture. A WRITE command can be initiated on any clock cycle following
a previous WRITE command. Full-speed random write accesses within a page can be
performed to the same bank, as shown in Figure 22 on page 33, or each subsequent
WRITE may be performed to a different bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and writes will
not be executed. An example is shown in Figure 23 on page 34. Data n + 1 is either the
last of a burst of two or the last desired element of a longer burst.
Figure 21:
WRITE-to-WRITE
Notes:
1. DQM is LOW. Each WRITE command may be to any bank.
Figure 22:
Random WRITE Cycles
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN
n + 1
DIN
b
DON’T CARE
TRANSITIONING DATA
DON’T CARE
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
a
DIN
x
DIN
m
WRITE
BANK,
COL a
BANK,
COL x
BANK,
COL m
TRANSITIONING DATA
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| MT48LC32M4A2TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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