參數(shù)資料
型號: MT48LC32M4A2P-7ELIT:G
元件分類: DRAM
英文描述: 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數(shù): 36/74頁
文件大?。?/td> 2385K
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
41
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
Table 8:
Truth Table 2 – CKE
Notes: 1–4
CKEn - 1 CKEn
Current State
Commandn
Actionn
Notes
L
Power-down
X
Maintain power-down
Self refresh
X
Maintain self refresh
Clock suspend
X
Maintain clock suspend
L
H
Power-down
COMMAND INHIBIT or NOP
Exit power-down
Self refresh
COMMAND INHIBIT or NOPX
Exit self refresh
Clock suspend
X
Exit clock suspend
H
L
All banks idle
COMMAND INHIBIT or NOP
Power-down entry
All banks idle
AUTO REFRESH
Self refresh entry
Reading or writing
WRITE or NOP
Clock suspend entry
H
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