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參數(shù)資料
| 型號： | MT48LC32M4A2P-7ELIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 25/74頁 |
| 文件大小： | 2385K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_2.fm - Rev. N 1/09 EN
31
1999 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 SDRAM
Operations
Figure 18:
Terminating a READ Burst
Notes:
1. DQM is LOW.
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 32.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge either is enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored (see Figure 20 on page 32). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE
NOP
T7
DON’T CARE
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE
NOP
X = 1 cycle
CL = 2
CL = 3
X = 2 cycles
TRANSITIONING DATA
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| MT48LC32M4A2TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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