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MPC8240 Integrated Processor User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 2
PowerPC Processor Core
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
2.2.5
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.3.1
2.2.6.3.2
2.2.6.3.3
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.2.1
2.3.1.2.2
2.3.1.2.3
2.3.1.2.4
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.3.1
2.4.2.3.2
2.4.3
2.4.3.1
Overview ..............................................................................................................2-1
PowerPC Processor Core Features ......................................................................2-3
Instruction Unit.................................................................................................2-5
Instruction Queue and Dispatch Unit...............................................................2-5
Branch Processing Unit (BPU).........................................................................2-6
Independent Execution Units ...........................................................................2-6
Integer Unit (IU)...........................................................................................2-6
Floating-Point Unit (FPU)............................................................................2-7
Load/Store Unit (LSU).................................................................................2-7
System Register Unit (SRU) ........................................................................2-7
Completion Unit...............................................................................................2-8
Memory Subsystem Support ............................................................................2-8
Memory Management Units (MMUs) .........................................................2-8
Cache Units ..................................................................................................2-8
Peripheral Logic Bus Interface.....................................................................2-9
Peripheral Logic Bus Protocol .................................................................2-9
Peripheral Logic Bus Data Transfers.......................................................2-9
Peripheral Logic Bus Frequency............................................................2-10
Programming Model...........................................................................................2-10
Register Set.....................................................................................................2-10
PowerPC Register Set ................................................................................2-11
MPC8240-Specific Registers.....................................................................2-13
Hardware Implementation-Dependent Register 0 (HID0).....................2-13
Hardware Implementation-Dependent Register 1 (HID1).....................2-17
Hardware Implementation-Dependent Register 2 (HID2).....................2-17
Processor Version Register (PVR).........................................................2-18
PowerPC Instruction Set and Addressing Modes...........................................2-18
Calculating Effective Addresses ................................................................2-18
PowerPC Instruction Set ............................................................................2-18
MPC8240 Implementation-Specific Instruction Set ..................................2-20
Cache Implementation........................................................................................2-20
PowerPC Cache Model...................................................................................2-21
MPC8240 Implementation-Specific Cache Implementation..........................2-21
Data Cache .................................................................................................2-21
Instruction Cache........................................................................................2-23
Cache Locking............................................................................................2-23
Entire Cache Locking.............................................................................2-23
Way Locking..........................................................................................2-23
Cache Coherency............................................................................................2-24
CCU Responses to Processor Transactions................................................2-24