MOTOROLA
Chapter 3. Signal Descriptions and Clocking
3-7
Detailed Signal Descriptions
3.1.2 Output Signal States at Reset
When a system reset is recognized (assertion of HRST_CPU and HRST_CTRL), the
MPC8240 aborts all current internal and external transactions, and releases all bidirectional
I/O signals to a high-impedance state. See Section 13.2.1, òSystem Reset,ó for a complete
description of the reset functionality.
There are 19 signals that serve alternate functions as reset conTguration input signals
during system reset. Their default values and the interpretation of their voltage levels during
reset are described in Section 3.4, òConTguration Pins Sampled at Reset.ó
On reset, the MPC8240 ignores most input signals (except for PCI_SYNC_IN and the reset
conTguration signals), and drives most of the output signals to an inactive state. Table 3-2
shows the states of the output-only signals that are not used as reset conTguration signals
during system reset.
3.2 Detailed Signal Descriptions
The following subsections describe the MPC8240 input and output signals, and the
meaning of their different states and relative timing information for assertion and negation.
In cases where signals serve multiple functions (and have multiple names), they are
described individually for each function.
3.2.1 PCI Interface Signals
This section provides descriptions of the PCI interface signals on the MPC8240. Note that
throughout this manual, signals and bits of the PCI interface are referenced in little-endian
Table 3-2. Output Signal States During System Reset
Interface
Signal
State During System Reset
PCI
GNT[3D0]
INTA
High impedance
Memory
CAS/DQM[0D7]
RAS/CS[0D7]
RCS1
SDRAS
SDCAS
WE
AS
Negated
SDMA[11D0]
SDMA12/SDBA1
SDBA0
High impedance
Clock
PCI_CLK[0D4]
PCI_SYNC_OUT
SDRAM_CLK[0D3]
SDRAM_SYNC_OUT
CKO
Driven
Test/ConTguration
TDO
Negated
