
11-16
MPC8240 Integrated Processor User's Manual
MOTOROLA
Programming Guidelines
programmed accordingly. For slave-mode data cycles (I2CSR[MAAS] = 0), I2CSR[SRW]
is not valid. I2CCR[MTX] should be read to determine the direction of the current transfer.
See Section 11.4.7, òInterrupt Service Routine Flowchart,ó for more details.
11.4.4 Generation of STOP
A data transfer ends with a STOP condition generated by the master device. A master
transmitter can generate a STOP condition after all the data has been transmitted.
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter
by not acknowledging the last byte of data, which is done by setting the transmit
acknowledge (I2CCR[TXAK]) bit before reading the next-to-last byte of data. For one-byte
transfers, a dummy read should be performed by the interrupt service routine. (See
Section 11.4.7, òInterrupt Service Routine Flowchart.ó) Before the interrupt service routine
reads the last byte of data, a STOP condition must Trst be generated by the MPC8240. The
MPC8240 automatically generates a STOP if I2CCR[TXAK] = 1.
11.4.5 Generation of Repeated START
At the end of a data transfer, if the master still wants to communicate on the bus, it can
generate another START condition followed by another slave address without Trst
generating a STOP condition by setting I2CCR[RSTA].
11.4.6 Slave Mode Interrupt Service Routine
In the slave interrupt service routine, the module addressed as a slave should be tested to
check if a calling of its own address has just been received. If I2CSR[MAAS] = 1, software
should set the transmit/receive mode select bit (I2CCR[MTX]) according to the R/W
command bit (I2CSR[SRW]). Writing to I2CCR clears I2CSR[MAAS] automatically. The
only time I2CSR[MAAS] is read as set is from the interrupt handler at the end of that
address cycle where an address match occurred; interrupts resulting from subsequent data
transfers will have I2CSR[MAAS] = 0. A data transfer can then be initiated by writing to
I2CDR for slave transmits or dummy reading from I2CDR in slave-receive mode. The slave
drives SCL low between byte transfers. SCL is released when the I2CDR is accessed in the
required mode.
11.4.6.1 Slave Transmitter and Received Acknowledge
In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be
tested before sending the next byte of data. The master signals an end-of-data by not
acknowledging the data transfer from the slave. When no acknowledge is received
(I2CSR[RXAK] = 1), the slave transmitter interrupt routine must clear I2CCR[MTX] to
switch the slave from transmitter to receiver mode. A dummy read of I2CDR then releases
SCL so that the master can generate a STOP condition. See also Section 11.4.7, òInterrupt
Service Routine Flowchart.ó