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MPC8240 Integrated Processor User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
12.9.7.2
12.9.7.3
12.9.7.4
12.9.7.5
12.9.8
12.9.8.1
12.9.8.2
12.9.8.3
12.9.8.4
12.9.9
12.9.9.1
12.9.9.2
12.9.10
Global Timer Current Count Registers (GTCCRs)..................................12-20
GlobalTimer Base Count Registers (GTBCRs) .......................................12-20
Global Timer Vector/Priority Registers (GTVPRs).................................12-21
Global Timer Destination Registers (GTDRs).........................................12-22
Direct, Serial, and Internal Interrupt Registers.............................................12-22
Direct & Serial Interrupt Vector/Priority Regs (IVPRs, SVPRs) ............12-22
Direct & Serial Interrupt Destination Registers (IDRs, SDRs)................12-24
Internal (I
2
C, DMA, I
2
O) Interrup
t
Vector/Priority Regs (IIVPRs)........12-24
Internal (I
2
C, DMA or I
2
O) Interrupt Destination Regs (IIDRs).............12-24
Processor-Related Registers.........................................................................12-24
Processor Current Task Priority Register (PCTPR).................................12-25
Processor Interrupt Acknowledge Register (IACK) ................................12-25
Processor End-of-Interrupt Register (EOI) ..................................................12-26
Chapter 13
Error Handling and Exceptions
13.1
13.1.1
13.1.2
13.2
13.2.1
13.2.2
13.2.3
13.2.3.1
13.2.3.2
13.2.3.3
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.2
13.3.2.1
13.3.2.2
13.3.2.3
13.3.2.4
13.3.3
13.3.3.1
13.3.3.2
13.3.3.3
13.3.3.4
13.3.3.5
13.4
Overview ............................................................................................................13-1
Error Handling Block Diagram......................................................................13-2
Priority of Externally-Generated Errors and Exceptions................................13-2
Exceptions and Error Signals .............................................................................13-3
System Reset ..................................................................................................13-3
Processor Core Error Signal (mcp).................................................................13-3
PCI Bus Error Signals ....................................................................................13-4
System Error (SERR).................................................................................13-4
Parity Error (PERR) ...................................................................................13-4
Nonmaskable Interrupt (NMI)....................................................................13-5
Error Reporting...................................................................................................13-5
Processor Interface .........................................................................................13-6
Processor Transaction Error.......................................................................13-6
Flash Write Error........................................................................................13-6
Memory Interface...........................................................................................13-6
System Memory Read Data Parity Error....................................................13-7
System Memory ECC Error.......................................................................13-7
System Memory Select Error.....................................................................13-7
System Memory Refresh Overflow Error..................................................13-8
PCI Interface...................................................................................................13-8
Address Parity Error...................................................................................13-8
Data Parity Error ........................................................................................13-8
Master-Abort Transaction Termination......................................................13-9
Received Target-Abort Error......................................................................13-9
NMI (Nonmaskable Interrupt)....................................................................13-9
Exception Latencies..........................................................................................13-10