
13-6
MPC8240 Integrated Processor User's Manual
MOTOROLA
Error Reporting
In addition to the error detection bits, the MPC8240 reports the assertion of NMI to the
processor core by asserting
mcp
(if enabled). Note that NMI assertion is not recorded in the
MPC8240's error detection bits. Reporting NMI assertion (by
mcp
) can be masked by any
error detection bits that are set.
13.3.1 Processor Interface
The processor interface of the MPC8240 detects unsupported processor bus transaction
errors and Flash write errors. In these cases, both ErrDR1[3] and ErrDR2[7] are cleared,
indicating that the error is due to a processor transaction and the address in the processor/
PCI error address register is valid. Internally, the MPC8240 asserts transfer acknowledge
(provided PICR1[10] = 0) to terminate the data tenure.
13.3.1.1 Processor Transaction Error
When a processor transaction error occurs, ErrDR1[1D0] is set to reect the error type.
Unsupported processor bus transactions include writes to the PCI interrupt-acknowledge
space (0xBFFF_FFFn using address map A or 0xFEFn_nnnn using address map B), and
attempts to execute the graphic read or graphic write instructions (
eciwx
or
ecowx
).
13.3.1.2 Flash Write Error
The MPC8240 allows writes to the system ROM space when PICR1[FLASH_WR_EN] is
set and PICR2[FLASH_WR_LOCKOUT] is cleared. Otherwise, any processor write
transaction to the system ROM space results in a Flash write error. When a Flash write error
occurs, ErrDR2[0] is set.
The ROM/Flash interface on the MPC8240 accommodates only single-beat, data-path
sized (8-, 32-, or 64-bit depending on the conTguration) writes to Flash memory. Software
must partition larger data into individual data path sized (8-, 32-, or 64-bit) write operations.
However, attempts to write to Flash with a data size other than the full data path size will
not cause a Flash write error.
13.3.2 Memory Interface
The memory interface of the MPC8240 detects read parity, ECC, memory select, and
refresh overow errors. The MPC8240 detects parity errors on the data bus during memory
(DRAM/EDO/SDRAM) read cycles. When MCCR2[ECC_EN] is set, the memory
controller can detect single-bit and multi-bit errors for system memory read transactions.
Since the ECC logic corrects single-bit errors, they are reported only when the number of
errors in the ECC single-bit error counter register equals the threshold value in the ECC
single-bit error trigger register. A memory select error occurs when a system memory
transaction address falls outside of the physical memory boundaries. A refresh overow
error occurs when no refresh transaction occurs within the equivalent of 16 refresh cycles.
In all cases, if the memory transaction is initiated by a PCI master, ErrDR1[3] is set; if the
memory transaction is initiated by the processor core, ErrDR1[3] is cleared.