
MOTOROLA
Chapter 7. Central Control Unit
7-5
Internal Buffers
Note
If a processor read from a PCI transaction is waiting for a
PCMWB snoop to complete (that is, data has been latched into
PRPRB from the PCI bus but has not yet returned to the
processorperhaps the processor must retry the read), all
subsequent requests for PCI writes to system memory will be
retried on the PCI bus.
The PCI interface of the MPC8240 continues to request the PCI bus until the processors
original request is completed. When the next processor transaction starts, the address is
snooped against the address of the previous transaction (in the internal address buffer) to
verify that the same data is being requested. Once all the requested data is latched, and all
PCI write to system memory snoops have completed, the CCU completes the data transfer
to the processor.
For example, if the processor initiates a critical-word-Trst burst read, starting with the
second double word of a cache line, the read on the PCI bus begins with the cache-line-
aligned address. If the PCI target disconnects after transferring the Trst half of the cache
line, the MPC8240 re-arbitrates for the PCI bus, and when granted, initiates a new
transaction with the address of the third double word of the line. If an alternate PCI master
requests data from system memory while the MPC8240 is waiting for the PCI bus grant,
the central control unit internally retries the processor core transaction to allow the PCI-
initiated transaction to be snooped by the processor core. When the processor snoop is
complete, the subsequent processor transaction is compared to the latched address and
attributes of the PRPRB to ensure that the processor is requesting the same data. Once all
data requested by the processor is latched in the PRPRB, the data is transferred to the
processor, completing the transaction.
7.1.2.2 Processor-to-PCI-Write Buffers (PRPWBs)
There are two 16-byte buffers for processor writes to PCI. These buffers can be used
together as one 32-byte buffer for processor burst writes to PCI, or separately for single-
beat writes to PCI. This allows the MPC8240 to support both burst transactions and streams
of single-beat transactions. The MPC8240 performs store gathering (if enabled) of
sequential accesses within the 16-byte range that makes up either the Trst or second half of
the cache line. All transfer sizes are gathered if enabled (PICR1[ST_GATH_EN] = 1).
The internal buffering minimizes the effect of the slower PCI bus on the higher-speed
peripheral logic bus that interfaces to the processor core. Once the processor write data is
latched internally, the internal peripheral logic bus is available for subsequent transactions
without having to wait for the write to the PCI target to complete. Note that both PCI
memory and I/O accesses are buffered. Device drivers must take into account that writes to
I/O devices on the PCI bus are posted. The processor may believe that the write has
completed while the MPC8240 is still trying to acquire mastership of the PCI bus.