
MOTOROLA
Index
Index-9
INDEX
CONFIG_DATA register,
5-2
,
8-21
configuration header summary,
5-8
,
8-19
PCI commands register,
5-10
,
8-19
status register,
5-11
,
8-19
retry PCI transactions,
8-15
signals
DEVSEL,
3-9
,
8-10
error reporting signals,
13-4
FRAME,
3-10
,
8-7
GNT,
3-10
,
8-4
IRDY,
3-12
,
8-7
LOCK,
3-12
,
8-26
PERR,
3-13
,
8-29
,
13-4
REQ,
3-11
,
8-4
SERR,
3-13
,
8-29
,
13-4
TRDY,
3-14
,
8-7
target-abort error,
8-16
,
13-9
target-disconnect,
7-4
,
8-3
,
8-15
target-initiated termination,
8-16
turnaround cycle,
8-11
PCI
interface
registers
CONFIG_ADDR register,
5-1
PCI_CLK (PCI clock),
3-30
PCI_SYNC_IN (PCI feedback clock),
3-31
PCI_SYNC_OUT (PCI clock synchronize out),
3-31
PCLSR (PCI cache line size register),
5-13
PCSRBAR (PCSR base address register),
5-14
Peripheral logic
block diagram,
1-11
bus interface,
2-9
bus operation,
1-10
control and status registers,
4-18
DMA controller,
1-15
features list,
1-11
major functional units,
1-12
overview,
1-10
power management modes,
1-18
PERR (PCI parity error) signal,
3-13
,
8-29
,
13-4
Phase locked loop,
14-5
PICRs (processor interface configuration registers)
PICR1 register
bit settings/overview,
5-22
CF_BREAD_WS bit,
5-22
FLASH_WR_EN bit,
5-23
,
13-6
LE_MODE (endian mode) bit,
5-23
MCP_EN bit,
3-26
,
13-4
speculative PCI reads bit,
5-24
ST_GATH_EN bit,
5-23
PICR2 register
bit settings/overview,
5-24
CF_APARK bit,
5-24
CF_APHASE_WS bit,
5-26
CF_SNOOP_WS bit,
5-25
FLASH_WR_LOCKOUT bit,
5-25
,
13-6
PIR (programming interface registers),
5-12
PLL_CFG (PLL configuration) signals,
3-29
PLTR (PCI latency timer register),
5-13
PMAA (PCI memory address attribute) signals,
3-28
Port X interface
block diagram,
6-72
overview,
6-72
Power management
doze mode,
14-4
doze, nap, sleep, DPM bits,
2-13
dynamic power management,
14-2
full-power mode,
14-4
nap mode,
8-26
,
14-5
overview,
1-17
,
14-1
PCI special-cycle operations,
8-25
peripheral logic programmable power modes,
1-18
PMCR registers
overview,
5-15
D
PMCR1
bit settings,
5-16
PM bit,
5-16
processor core,
14-1
programmable power modes,
1-18
,
14-2
,
14-8
sleep mode,
5-16
,
14-5
software considerations,
14-6
Power-on reset
configuration pins sampled,
3-35
intialization at power-on reset (POR),
13-3
memory interface configuration,
6-6
output signal state,
3-7
SDRAM initialization,
6-46
PowerPC architecture
instruction list,
A-1
,
A-9
,
A-17
instruction set,
2-18
Processor control instructions,
A-24
Processor core
block diagram,
2-2
bus error signals,
13-3
bus error status register,
13-5
byte ordering,
B-1
cache implementation,
2-20
cache units,
2-8
configuration registers,
5-22
control and status registers,
4-17
,
4-17
differences with the MPC8240,
2-34
dispatch unit,
2-5
error detection,
13-6
execution units,
2-6
features list,
2-3
floating-point unit,
2-7
instruction queue,
2-5
instruction timing,
2-33
instruction unit,
2-5
integer unit,
2-6
memory management unit,
2-8
,
2-31