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MPC8240 Integrated Processor User's Manual
MOTOROLA
Peripheral Logic Overview
1.4.6.3 Intelligent Input/Output Controller (I
2
O)
The intelligent I/O speciTcation is an open standard that deTnes an abstraction layer
interface between the OS and subsystem drivers. Messages are passed between the message
abstraction layer from one device to another.
The I
2
O speciTcation describes a system as being made up of host processors and input/
output platforms (IOPs). The host processor is a single processor or a collection of
processors working together to execute a homogenous operating system. An IOP consists
of a processor, memory, and I/O interfaces. The IOP functions separately from other
processors within the system to handle system I/O functions.
The I
2
O controller of the MU enhances communication between hosts and IOPs within a
system. The MU maintains a set of FIFO buffers located in local IOP memory. Four queues
are provided: two for inbound messages and two for outbound messages. The inbound
message queues are used to transfer messages from a remote host or IOP to the processor
core. The outbound queues are used to transfer messages from the processor core to the
remote host. Messages are transferred between the host and the IOP using PCI memory-
mapped registers. The MPC8240s I
2
O controller facilitates moving the messages to and
from the inbound and outbound registers and local IOP memory. Interrupts signal the host
and IOP to indicate the arrival of new messages.
1.4.7 Inter-Integrated Circuit (I
2
C) Controller
The I
2
C serial interface has become an industry de-facto standard for communicating with
low-speed peripherals. Typically, it is used for system management functions and
EEPROM support. The MPC8240 contains an I
2
C controller with full master and slave
functionality.
1.4.8 Embedded Programmable Interrupt Controller (EPIC)
The integrated hardware interrupt controller reduces the overall component count in
embedded applications. The embedded programmable interrupt controller (EPIC) is
designed to collect external and internal hardware interrupts, prioritize them, and deliver
them to the processor core.
The module operates in two modes:
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In direct mode, Tve level- or edge-triggered interrupts can be connected directly to
an MPC8240.
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The MPC8240 provides a serial delivery mechanism for when more than Tve
external interrupt sources are needed. The serial mechanism allows for up to 16
interrupts to be serially scanned into the MPC8240. This mechanism increases the
number of interrupts without increasing the number of pins.
The outbound interrupt request signal, L_INT, is used to signal interrupts to the host
processor when the MPC8240 is conTgured for agent mode. The MPC8240 EPIC includes
four programmable timers that can be used for system timing or for generating periodic
interrupts.