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MPC8240 Integrated Processor User's Manual
MOTOROLA
ILLUSTRATIONS
Figure
Number
15-12
Title
Page
Number
Example SDRAM Debug Address, MIV, and MAA Timings for Burst Read
Operation........................................................................................................15-12
Example SDRAM Debug Address, MIV, and MAA Timings for Burst Write
Operation........................................................................................................15-13
Example ROM Debug Address, MIV, and MAA Timings For Burst Read....15-14
Example Flash Debug Address, MIV, and MAA Timings For Single-Byte
Read...............................................................................................................15-15
Example Flash Debug Address, MIV, and MAA Timings for Write
Operation........................................................................................................15-16
Functional Diagram of Memory Data Path Error Injection.............................15-17
Data High Error Injection Mask (MDP_ERR_INJ_MASK_DH): 4Bytes @
<FF000, F00> ................................................................................................15-18
Data Low Error Injection Mask (MDP_ERR_INJ_MASK_DL): 4Bytes @
<FF004, F04> ................................................................................................15-18
Parity Error Injection Mask (MDP_ERR_INJ_MASK_PAR): 4Bytes @
<FF008, F08> ................................................................................................15-19
Data High Error Capture Monitor (MDP_ERR_CAP_MON_DH): 4Bytes @
<FF00c, F0c>.................................................................................................15-20
Data Low Error Capture Monitor (MDP_ERR_CAP_MON_DL): 4Bytes @
<FF010, F10> ................................................................................................15-20
Parity Error Capture Monitor (MDP_ERR_CAP_MON_PAR): 4Bytes @
<FF014, F14> ................................................................................................15-21
JTAG Interface Block Diagram.......................................................................15-22
Four-Byte Transfer to PCI Memory SpaceBig-Endian Mode..........................B-3
Big-Endian Memory Image in Local Memory.....................................................B-4
Big-Endian Memory Image in Big-Endian PCI Memory Space..........................B-5
Munged Memory Image in local memory............................................................B-7
Little-Endian Memory Image in Little-Endian PCI Memory Space....................B-8
One-Byte Transfer to PCI Memory SpaceLittle-Endian Mode........................B-9
Two-Byte Transfer to PCI Memory SpaceLittle-Endian Mode.....................B-10
Four-Byte Transfer to PCI Memory SpaceLittle-Endian Mode.....................B-11
One-Byte Transfer to PCI I/O SpaceLittle-Endian Mode..............................B-12
Two-Byte Transfer to PCI I/O SpaceLittle-Endian Mode .............................B-13
Four-Byte Transfer to PCI I/O SpaceLittle-Endian Mod...............................B-14
15-13
15-14
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
15-23
15-24
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
B-10
B-11