
MOTOROLA
Index
Index-3
INDEX
memory debug address,
1-19
overview,
15-1
parity error capture monitor register,
15-20
parity error injection mask register,
15-19
PCI address attribute signals,
15-2
Decrementer interrupt,
14-2
Device drivers, posted writes,
7-5
DEVSEL (device select) signal,
3-9
,
8-10
DH
n
/DL
n
(data bus) signals,
3-18
Disconnect,
7-4
,
8-3
,
8-15
DMA burst wrap,
6-22
DMA controller,
1-15
block diagram,
9-2
coherency,
9-5
DMA descriptors,
9-8
local memory to local memory transfers,
9-6
local memory to PCI,
9-6
modes
chaining mode,
9-4
direct mode,
9-4
operation,
9-3
overview,
9-1
PCI to local memory transfers,
9-6
PCI to PCI transfers,
9-6
register summary,
9-2
transfer types,
9-6
DMR (DMA mode register),
9-12
Doorbell registers
I
2
O interface,
10-2
overview,
1-15
Doze mode,
1-18
DQM
n
(SDRAM data qualifier) signals,
3-17
DSR (DMA status register),
9-14
E
ECC single-bit error
registers,
5-26
,
13-6
EDO DRAM interface
address multiplexing,
6-11
block diagram,
6-6
data interface,
6-14
DMA burst wrap,
6-22
ECC,
6-24
initialization,
6-16
organizations supported,
6-9
overview,
6-6
page mode retention,
6-23
parity,
6-23
power saving modes,
6-29
refresh timing,
6-28
RMW parity,
6-23
timing,
6-17
Effective address calculations,
2-18
Embedded utilities memory block,
4-16
Emulation mode
emulation support,
8-31
ESCR1/ESCR2 registers,
5-33
EPIC controller
block diagram,
12-3
EPIC vendor identification,
12-17
external interrupt source destination register,
12-24
external interrupt source vector register,
12-22
features list,
12-2
FPR,
12-15
global configuration register,
12-15
global timer base count,
12-20
global timer current count register,
12-20
global timer destination register,
12-22
global timer vector priority register,
12-21
internal block diagram,
12-8
internal interrupt destination register,
12-24
internal interrupt vector priority register,
12-24
interrupt protocol,
12-7
overview,
1-16
,
12-1
pass-through capability,
12-10
processor current task priority register,
12-25
processor initialization,
12-18
processor interrupt acknowledge register,
12-25
programming interface,
12-13
registers,
12-15
registers not visible to the programmer
IPR,
12-9
IRR,
12-9
IS,
12-9
ISR,
12-9
serial interrupt configuration register,
12-16
serial interrupt interface,
12-10
serial interrupt source destination register,
12-24
signals,
12-2
spurious vector register,
12-18
timer frequency reporting register,
12-19
timers,
12-12
EPIC vendor identification register,
12-17
ErrDR1/ErrDR2 (error detection) registers,
5-29
,
8-28
,
13-5
ErrEnR1/ErrEnR2 (error enabling) registers,
5-27
Errors
EDO ECC,
6-24
error detection registers,
5-29
,
8-28
,
13-5
error enabling registers,
5-27
error handling
overview,
13-1
registers,
3-26
,
5-26
,
8-28
,
13-3
error reporting,
13-6
address/data error,
8-16
,
13-8
error detection registers,
5-29
,
8-28
,
13-5
errors within a nibble,
13-7
Flash write error,
13-6
master-abort transaction termination,
8-15
,
13-9