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MPC8240 Integrated Processor User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
3.2.7.7
3.2.7.8
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
SDRAM Feedback Clock (SDRAM_SYNC_IN)Input..........................3-31
Debug Clock (CKO)Output....................................................................3-31
Clocking
.............................................................................................................3-32
Clocking Method............................................................................................3-32
DLL Operation and Locking..........................................................................3-33
Clock Synchronization ...................................................................................3-34
Clocking System Solution Examples .............................................................3-34
Configuration Pins Sampled at Reset.................................................................3-35
Chapter 4
Address Maps
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.4
4.4.1
4.4.2
Address Map A.....................................................................................................4-1
Address Map B.....................................................................................................4-5
Address Translation............................................................................................4-10
Inbound PCI Address Translation..................................................................4-10
Outbound PCI Address Translation................................................................4-11
Address Translation Registers........................................................................4-12
Local Memory Base Address Register (LMBAR).....................................4-13
Inbound Translation Window Register (ITWR) ........................................4-14
Outbound Memory Base Address Register (OMBAR)..............................4-15
Outbound Translation Window Register (OTWR)....................................4-15
Embedded Utilities Memory Block (EUMB).....................................................4-16
Processor Core Control and Status Registers.................................................4-17
Peripheral Control and Status Registers.........................................................4-18
Chapter 5
Configuration Registers
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.2
5.1.3
5.1.4
5.1.4.1
5.1.5
5.1.5.1
5.1.5.2
5.1.6
5.2
Configuration Register Access.............................................................................5-1
Processor Access to Configuration Registers (Map A)....................................5-1
Indirect Access Method...............................................................................5-1
Direct Access Method..................................................................................5-2
Processor Access to Configuration Registers (Map B)....................................5-2
PCI Access to Configuration Registers............................................................5-2
Configuration Register Access in Little-Endian Mode....................................5-2
Configuration Register Access in Big-Endian Mode...................................5-3
Configuration Register Summary.....................................................................5-4
Processor-Accessible Configuration Registers ............................................5-4
PCI-Accessible Configuration Registers......................................................5-6
Configuration Register Order...........................................................................5-8
PCI Interface Configuration Registers .................................................................5-8