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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC68HC11F1CPU4 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 72/158闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 512 EEPROM 4MHZ 80-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | HC11 |
| 鏍稿績铏曠悊鍣細 | HC11 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | SCI锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 30 |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| EEPROM 澶�?銆�?/td> | 512 x 8 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.75 V ~ 5.25 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 80-LQFP |
| 鍖呰锛� | 鎵樼洡 |
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PIN DESCRIPTIONS
MC68HC11F1
2-6
TECHNICAL DATA
2.8 MODA and MODB (MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes. Refer to SEC-
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that execution of an instruction has begun. The LIR pin is configured for
wired-OR operation (only pulls low). A series of E-clock cycles occurs during execution
of each instruction. The LIR signal is asserted (drives low) during the first E-clock cycle
of each instruction (opcode fetch). This output is provided for assistance in program
debugging.
The VSTBY pin is used to input RAM standby power. The MCU is powered from the
VDD signal unless the difference between the level of VSTBY and Vdd is greater than
one MOS threshold (about 0.7 volts). When these voltages differ by more than 0.7
volts, the internal 768-byte RAM and part of the reset logic are powered from VSTBY
rather than VDD. This allows RAM contents to be retained without VDD power applied
to the MCU. Reset must be driven low before VDD is removed and must remain low
until VDD has been restored to a valid level.
2.9 VRH and VRL
These pins provide the reference voltage for the analog-to-digital converter. Bypass
capacitors should be used to minimize noise on these signals. Any noise on VRH and
VRL will directly affect A/D accuracy.
2.10 R/W
In expanded and test modes, R/W indicates the direction of transfers on the external
data bus. A logic level one on this pin indicates that a read cycle is in progress. A logic
zero on this pin indicates that a write cycle is in progress and that no external device
should drive the data bus.
The E-clock can be used to enable external devices to drive data onto the data bus
during the second half of a read bus cycle (E clock high). R/W can then be used to
control the direction of data transfers. R/W drives low when data is being written to the
external data bus. R/W will remain low during consecutive data bus write cycles, such
as when a double-byte store occurs.
2.11 Port Signals
For the MC68HC11F1, 54 pins are arranged into six 8-bit ports: A, B, C, E, F, and G,
and one 6-bit port (D). Each of these seven ports serves a purpose other than I/O, de-
pending on the operating mode or peripheral functions selected. Note that ports B, C,
and F are available for I/O functions only in single-chip and bootstrap modes. The pins
of ports A, C, D, and G are fully bidirectional. Ports B and F are output-only ports. Port
E is an input-only port. Refer to Table 2-1 for details about the 54 port signals鈥� func-
tions within different operating modes.
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For More Information On This Product,
Go to: www.freescale.com
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鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68HC11F1CPU5 | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:Technical Summary 8-Bit Microcontroller |
| MC68HC11F1CPUE5 | 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪: |
| MC68HC11F1FB | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ROM-based high-performance microcontrollers |
| MC68HC11F1FB1 | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ROM-based high-performance microcontrollers |
| MC68HC11F1FB3 | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ROM-based high-performance microcontrollers |
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