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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC68HC11F1CPU4 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 122/158闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 512 EEPROM 4MHZ 80-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | HC11 |
| 鏍稿績铏曠悊鍣細 | HC11 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | SCI锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 30 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | ROMless |
| EEPROM 澶�?銆�?/td> | 512 x 8 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.75 V ~ 5.25 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 80-LQFP |
| 鍖呰锛� | 鎵樼洡 |
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RESETS AND INTERRUPTS
MC68HC11F1
5-4
TECHNICAL DATA
CR[1:0] 鈥� COP Timer Rate Select
The internal E clock is first divided by 215 before it enters the COP watchdog system.
These control bits determine a scaling factor for the watchdog timer. Refer to Table 5-
5.1.6 CONFIG Register
P indicates a previously programmed bit. P(L) indicates that the bit resets to the logic
level held in the latch prior to reset, but the function of COP is controlled by DISR in
TEST1 register.
EE[3:0] 鈥� EEPROM Mapping Control
Bit 3 鈥� Not implemented
Always reads one
NOCOP 鈥� COP System Disable
0 = COP system enabled (forces reset on time-out)
1 = COP system disabled
Bit 1 鈥� Not implemented
Always reads one
EEON 鈥� EEPROM Enable
5.2 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
These initial states then control on-chip peripheral systems to force them to known
start-up states, as follows:
CONFIG 鈥� System Configuration Register
$103F
Bit 7
654321
Bit 0
EE3
EE2
EE1
EE0
鈥�
NOCOP
鈥�
EEON
RESET:
11111
P
11
Single Chip
11111
P(L)
1
Bootstrap
P
P1P1P
Expanded
PPPP
1
P(L)
1
0
Special Test
Table 5-2 Reset Cause, Operating Mode, and Reset Vector
Cause of Reset
Normal Mode Vector
Special Test or Bootstrap
POR or RESET Pin
$FFFE, FFFF
$BFFE, $BFFF
Clock Monitor Failure
$FFFC, FFFD
$BFFC, $BFFD
COP Watchdog Time-out
$FFFA, FFFB
$BFFA, $BFFB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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鐩搁棞(gu膩n)PDF璩囨枡 |
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鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68HC11F1CPU5 | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:Technical Summary 8-Bit Microcontroller |
| MC68HC11F1CPUE5 | 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪: |
| MC68HC11F1FB | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ROM-based high-performance microcontrollers |
| MC68HC11F1FB1 | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ROM-based high-performance microcontrollers |
| MC68HC11F1FB3 | 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ROM-based high-performance microcontrollers |
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