參數(shù)資料
型號： MC68HC11F1CPU4
廠商： Freescale Semiconductor
文件頁數(shù)： 124/158頁
文件大?。?/td> 0K
描述： IC MCU 512 EEPROM 4MHZ 80-LQFP
標準包裝： 90
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉換器： A/D 8x8b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-LQFP
包裝： 托盤
RESETS AND INTERRUPTS
MC68HC11F1
5-6
TECHNICAL DATA
5.2.6 Pulse Accumulator
The pulse accumulator system is disabled at reset so that the pulse accumulator input
(PAI) pin defaults to being a general-purpose input pin.
5.2.7 Computer Operating Properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis-
ter is cleared, and disabled if NOCOP is set. The COP rate is set for the shortest du-
ration time-out.
5.2.8 Serial Communications Interface (SCI)
The reset condition of the SCI system is independent of the operating mode. All trans-
mit and receive interrupts are masked and both the transmitter and receiver are dis-
abled so the port pins default to being general-purpose I/O lines. The SCI frame format
is initialized to an 8-bit character size. The send break and receiver wakeup functions
are disabled. The TDRE and TC status bits in the SCI status register are both set, in-
dicating that there is no transmit data in either the transmit data register or the transmit
serial shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status
bits are cleared.
5.2.9 Serial Peripheral Interface (SPI)
The SPI system is disabled by reset. The port pins associated with this function default
to being general-purpose I/O lines.
5.2.10 Analog-to-Digital Converter
The A/D converter configuration is indeterminate after reset. The ADPU bit is cleared
by reset, which disables the A/D system. The conversion complete flag is cleared by
reset.
5.2.11 System
The EEPROM programming controls are disabled, so the memory system is config-
ured for normal read operation. PSEL[3:0] are initialized with the binary value %0101,
causing the external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin is
configured for level-sensitive operation (for wired-OR systems). The RBOOT, SMOD,
and MDA bits in the HPRIO register reflect the status of the MODB and MODA inputs
at the rising edge of reset. The DLY control bit is set to specify that an oscillator start-
up delay is imposed upon recovery from STOP mode. The clock monitor system is dis-
abled because CME and FCME are cleared.
5.3 Reset and Interrupt Priority
Resets and interrupts have a hardware priority that determines which reset or interrupt
is serviced first when simultaneous requests occur. Any maskable interrupt can be giv-
en priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is as follows:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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