參數(shù)資料
型號： MC68HC11F1CPU4
廠商： Freescale Semiconductor
文件頁數(shù)： 37/158頁
文件大小： 0K
描述： IC MCU 512 EEPROM 4MHZ 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-LQFP
包裝： 托盤
ANALOG-TO-DIGITAL CONVERTER
TECHNICAL DATA
10-7
10.7 Operation in STOP and WAIT Modes
If a conversion sequence is in progress when either the STOP or WAIT mode is en-
tered, the conversion of the current channel is suspended. When the MCU resumes
normal operation, that channel is resampled and the conversion sequence is resumed.
As the MCU exits the WAIT mode, the A/D circuits are stable and valid results can be
obtained on the first conversion. However, in STOP mode, all analog bias currents are
disabled and it is necessary to allow a stabilization period when leaving the STOP
mode. If the STOP mode is exited with a delay (DLY = 1), there is enough time for
these circuits to stabilize before the first conversion. If the STOP mode is exited with
no delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D circuitry to stabilize
to avoid invalid results.
10.8 A/D Control/Status Registers
All bits in this register can be read or written, except CCF (bit 7), which is a read-only
status indicator, and bit 6, which always reads as zero. Write to ADCTL to initiate a
conversion. To quit a conversion in progress, write to this register and a new conver-
sion sequence begins immediately.
CCF — Conversions Complete Flag
A read-only status indicator, this bit is set when all four A/D result registers contain val-
id conversion results. Each time the ADCTL register is overwritten, this bit is automat-
ically cleared to zero and a conversion sequence is started. In the continuous mode,
CCF is set at the end of the first conversion sequence.
Bit 6 — Not implemented
Always reads zero
SCAN — Continuous Scan Control
When this control bit is clear, the four requested conversions are performed once to
fill the four result registers. When this control bit is set, conversions continue in a
round-robin fashion with the result registers updated as data becomes available.
MULT — Multiple Channel/Single Channel Control
When this bit is clear, the A/D converter system is configured to perform four consec-
utive conversions on the single channel specified by the four channel select bits CD–
CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D system is configured
to perform a conversion on each of four channels where each result register corre-
sponds to one channel.
ADCTL — A/D Control/Status
$1030
Bit 7
654321
Bit 0
CCF
—
SCAN
MULT
CD
CC
CB
CA
RESET:
1
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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