參數(shù)資料
型號: MC68HC11F1CPU4
廠商: Freescale Semiconductor
文件頁數(shù): 20/158頁
文件大?。?/td> 0K
描述: IC MCU 512 EEPROM 4MHZ 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 4MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲器類型: ROMless
EEPROM 大小: 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
TIMING SYSTEM
MC68HC11F1
9-10
TECHNICAL DATA
OM[2:5] — Output Mode
OL[2:5] — Output Level
These control bit pairs are encoded to specify the action taken after a successful OCx
compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to
Table 9-3 for the coding.
9.3.7 Timer Interrupt Mask Register 1
Use this 8-bit register to enable or inhibit the timer input capture and output compare
interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt se-
quence is requested.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When
I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence
is requested.
NOTE
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
TCTL1 — Timer Control 1
$1020
Bit 7
654321
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
0000000
0
Table 9-2 Timer Output Compare Configuration
OMx
OLx
Action Taken on Successful Compare
0
Timer disconnected from output pin logic
0
1
Toggle OCx output line
1
0
Clear OCx output line to zero
1
Set OCx output line to one
TMSK1 — Timer Interrupt Mask 1
$1022
Bit 7
654321
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
RESET:
0000000
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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