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參數(shù)資料
| 型號： | MC68HC11F1CPU4 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 129/158頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 512 EEPROM 4MHZ 80-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 30 |
| 程序存儲器類型： | ROMless |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 托盤 |
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RESETS AND INTERRUPTS
MC68HC11F1
5-10
TECHNICAL DATA
at the address specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are pulled from the
stack in reverse order so that normal program execution can resume. Refer to SEC-
TION 3 CENTRAL PROCESSING UNIT for further information.
5.4.2 Non-Maskable Interrupt Request (XIRQ)
Non-maskable interrupts are useful because they can always interrupt CPU opera-
tions. The most common use for such an interrupt is for serious system problems, such
as program runaway or power failure. The XIRQ input is an updated version of the NMI
input of earlier MCUs.
Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable interrupts
and XIRQ. After minimum system initialization, software can clear the X bit by a TAP
instruction, enabling XIRQ interrupts. Thereafter, software cannot set the X bit. Thus,
an XIRQ interrupt is a nonmaskable interrupt. Because the operation of the I-bit-relat-
ed interrupt structure has no effect on the X bit, the internal XIRQ pin remains non-
masked. In the interrupt priority logic, the XIRQ interrupt has a higher priority than any
source that is maskable by the I bit. All I-bit-related interrupts operate normally with
their own priority relationship.
When an I-bit-related interrupt occurs, the I bit is automatically set by hardware after
stacking the CCR byte. The X bit is not affected. When an X-bit-related interrupt oc-
curs, both the X and I bits are automatically set by hardware after stacking the CCR.
A return from interrupt instruction restores the X and I bits to their pre-interrupt request
state.
5.4.3 Illegal Opcode Trap
Because not all possible opcodes or opcode sequences are defined, the MCU in-
cludes an illegal opcode detection circuit, which generates an interrupt request. When
an illegal opcode is detected and the interrupt is recognized, the current value of the
program counter is stacked. After interrupt service is complete, reinitialize the stack
pointer so repeated execution of illegal opcodes does not cause stack underflow. Left
uninitialized, the illegal opcode vector can point to a memory location that contains an
illegal opcode. This condition causes an infinite loop that causes stack underflow. The
stack grows until the system crashes.
Table 5-5 Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP
PCL
SP – 1
PCH
SP – 2
IYL
SP – 3
IYH
SP – 4
IXL
SP – 5
IXH
SP – 6
ACCA
SP – 7
ACCB
SP – 8
CCR
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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