參數(shù)資料
型號： MC68HC11F1CPU4
廠商： Freescale Semiconductor
文件頁數(shù)： 150/158頁
文件大?。?/td> 0K
描述： IC MCU 512 EEPROM 4MHZ 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 30
程序存儲器類型： ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-LQFP
包裝： 托盤
SERIAL COMMUNICATIONS INTERFACE
TECHNICAL DATA
7-5
7.5 SCI Error Detection
Three error conditions, SCDR overrun, received bit noise, and framing can occur dur-
ing generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial com-
munications status register (SCSR) indicate if one of these error conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from the
receive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When
an overrun error occurs, the data that caused the overrun is lost and the data that was
already in SCDR is not disturbed. The OR is cleared when the SCSR is read (with OR
set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the
start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared
when the SCSR is read (with FE equal to one) followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing error (FE) bit
is set. FE is set at the same time as the RDRF. If the byte received causes both fram-
ing and overrun errors, the processor only recognizes the overrun error. The framing
error flag inhibits further transfer of data into the SCDR until it is cleared. The FE bit is
cleared when the SCSR is read (with FE equal to one) followed by a read of the SCDR.
7.6 SCI Registers
There are five addressable registers associated with the SCI. SCCR1, SCCR2, and
BAUD are control registers. SCDR is the SCI data register and SCSR is the SCI status
register. Refer to the BAUD register description as well as the block diagram for the
baud rate generator.
7.6.1 Serial Communications Data Register
SCDR is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the re-
ceive data buffer and writes access the transmit data buffer. Receive and transmit are
double buffered.
7.6.2 Serial Communications Control Register 1
The SCCR1 register provides the control bits that determine word length and select
the method used for the wakeup feature.
SCDR — SCI Data Register
$102F
Bit 7
654321
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
RESET:
IIIIIII
I
SCCR1 — SCI Control Register 1
$102C
Bit 7
654321
Bit 0
R8
T8
—
M
WAKE
—
RESET:
I
00000
0
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
MC68HRC908JK3CDW IC MCU 4K FLASH 8MHZ SO20
MC68HC711K4CFU4 IC MCU 24K 4MHZ EEPROM 80-QFP
MC68HC11K1CFN4 IC MCU 640 EEPROM 4MHZ 84-PLCC
MC68332ACFC20B1 IC MCU 32BIT 20MHZ 132-PQFP
MC68332GCFC16 IC MCU 32BIT 16MHZ 132-PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC11F1CPU5 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary 8-Bit Microcontroller
MC68HC11F1CPUE5 制造商:Freescale Semiconductor 功能描述:
MC68HC11F1FB 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers
MC68HC11F1FB1 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers
MC68HC11F1FB3 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*