參數(shù)資料
型號: MC68HC11F1CPU4
廠商: Freescale Semiconductor
文件頁數(shù): 142/158頁
文件大小: 0K
描述: IC MCU 512 EEPROM 4MHZ 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 4MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲器類型: ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
PARALLEL INPUT/OUTPUT
MC68HC11F1
6-4
TECHNICAL DATA
Bits [7:6] — Not implemented
Always read zero
DDD[5:0] — Data Direction for Port D
0 = Input
1 = Output
NOTE
When the SPI system is in slave mode, DDD5 has no meaning nor
effect. When the SPI system is in master mode, DDD5 determines
whether bit 5 of PORTD is an error detect input (DDD5 = 0) or a gen-
eral-purpose output (DDD5 = 1). If the SPI system is enabled and ex-
pects any of bits [4:2] to be an input, that bit will be an input
regardless of the state of the associated DDR bit. If any of bits [4:2]
are expected to be outputs that bit will be an output only if the asso-
ciated DDR bit is set.
6.5 Port E
Port E has eight general-purpose input pins and shares functions with the A/D convert-
er system. When some port E pins are being used for general-purpose input and oth-
ers are being used as A/D inputs, PORTE should not be read during the sample
portion of an A/D conversion.
6.6 Port F
Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are gen-
eral-purpose outputs. In expanded and test modes, port F pins are low order address
outputs and PORTF is not in the memory map.
DDRD — Data Direction Register for Port D
$1009
Bit 7
654321
Bit 0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
RESET:
0000000
0
PORTE — Port E Data
$100A
Bit 7
654321
Bit 0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
IIIIIII
I
Alt. Pin
Func.:
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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