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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC68HC11F1CPU4 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 52/158闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 512 EEPROM 4MHZ 80-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | HC11 |
| 鏍稿績铏曠悊鍣細 | HC11 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | SCI锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 30 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | ROMless |
| EEPROM 澶�?銆�?/td> | 512 x 8 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.75 V ~ 5.25 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 80-LQFP |
| 鍖呰锛� | 鎵樼洡 |
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ELECTRICAL CHARACTERISTICS
TECHNICAL DATA
A-11
NOTES:
1. For fop < 2 MHz, source impedances should equal approximately 10 k. For fop 鈮� 2 MHz, source impedances
should equal approximately 5 k
鈥� 10 k. Source impedances greater than 10 k affect accuracy adversely be-
cause of input leakage.
2. Performance verified down to 2.5 V
V
R, but accuracy is tested and guaranteed at VR = 5 V 卤 10%
Table A-6 Analog-To-Digital Converter Characteristics
VDD = 5.0 Vdc 卤 5%, VSS = 0 Vdc, TA = TL to TH, 750 kHz 鈮� E 鈮� 3.0 MHz, unless otherwise noted
Characteristic
Parameter
Min
Absolute
2.0 MHz 3.0 MHz 4.0 MHz Unit
Max
Resolution
Number of Bits Resolved by A/D Converter
鈥�
8
鈥�
Bits
Non-Linearity
Maximum Deviation from the Ideal A/D Transfer
Characteristics
鈥斺€�
卤 1
LSB
Zero Error
Difference Between the Output of an Ideal and
an Actual for Zero Input Voltage
鈥斺€�
卤 1
LSB
Full Scale Error
Difference Between the Output of an Ideal and
an Actual A/D for Full-Scale Input Voltage
鈥斺€�
卤 1
LSB
Total Unadjusted
Error
Maximum Sum of Non-Linearity, Zero Error, and
Full-Scale Error
鈥斺€�
卤 1/2
卤 1 1/2 卤 1 1/2 LSB
Quantization
Error
Uncertainty Because of Converter Resolution
鈥�
卤 1/2
LSB
Absolute
Accuracy
Difference Between the Actual Input Voltage and
the Full-Scale Weighted Equivalent of the Binary
Output Code, All Error Sources Included
鈥斺€�
卤 1
卤 2
LSB
Conversion
Range
Analog Input Voltage Range
VRL
鈥擵RH
VRH
V
VRH
Maximum Analog Reference Voltage
(Note 2)
VRL
鈥擵DD +
0.1
VDD +
0.1
VDD +
0.1
V
VRL
Minimum Analog Reference Voltage
(Note 2)
VSS 鈥�0.1
鈥�
VRH
V
R
Minimum Difference between VRH and VRL
(Note 2)
3
鈥�
鈥斺€斺€�
V
Conversion
Time
Total Time to Perform a Single
Analog-to-Digital Conversion:
E Clock
Internal RC Oscillator
鈥�
32
鈥�
tcyc + 32
鈥�
tcyc + 32
鈥�
tcyc + 32
tcyc
s
Monotonicity
Conversion Result Never Decreases with an
Increase in Input Voltage and has no Missing
Codes
Guaranteed
Zero Input
Reading
Conversion Result when Vin = VRL
00
鈥�
Hex
Full Scale
Reading
Conversion Result when Vin = VRH
鈥�
FF
Hex
Sample
Acquisition Time
Analog Input Acquisition Sampling Time:
E Clock
Internal RC Oscillator
鈥�
12
鈥�
12
鈥�
12
鈥�
12
tcyc
s
Sample/Hold
Capacitance
Input Capacitance during Sample PE[7:0]
鈥�
20 (Typ)
鈥�
pF
Input Leakage
Input Leakage on A/D Pins
PE[7:0]
VRL, VRH
鈥�
400
1.0
400
1.0
400
1.0
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A
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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